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# Architecture description of an unsegmented (all wires span only one logic 
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# block) architecture.
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# Uniform channels.  Each pin appears on only one side.
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io_rat 2
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chan_width_io 1
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chan_width_x uniform 1 
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chan_width_y uniform 1
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# 4-input LUT.  LUT inputs first, then output, then clock.
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inpin class: 0 bottom 
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inpin class: 0 left
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inpin class: 0 top
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inpin class: 0 right
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outpin class: 1 bottom
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inpin class: 2 top                  # Clock; shouldn't matter.
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# Class 0 is LUT inputs, class 1 is the output, class 2 is the clock.
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# Information about what's in a cluster.  Always required by the parser,
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# but the information isn't used yet.  It will be used when timing
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# analysis is added.
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subblocks_per_cluster 1
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subblock_lut_size 4
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#parameters needed only for detailed routing.
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#switch_block_type wilton
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#switch_block_type universal
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switch_block_type subset
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Fc_type fractional
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Fc_output 1
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Fc_input 1
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Fc_pad 1
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segment frequency: .6 length: 1 wire_switch: 0 opin_switch: 2 Frac_cb: 1. \
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         Frac_sb: 1. Rmetal: 5 Cmetal: 5e-15
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segment frequency: .2 length: 2 wire_switch: 1 opin_switch: 1 \
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         Frac_cb: 1. Frac_sb: 1 Rmetal: 5 Cmetal: 5e-15
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segment frequency: .2 length: 4 wire_switch: 1 opin_switch: 1 \
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         Frac_cb: 1. Frac_sb: 1 Rmetal: 5 Cmetal: 5e-15
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switch 0  buffered: no  R: 50 Cin: 4e-15  Cout: 4e-15 Tdel: 1e-11
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switch 1  buffered: yes  R: 40  Cin: .5e-15  Cout: 8e-15  Tdel: 5e-11
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switch 2  buffered: yes  R: 80  Cin: .5e-15  Cout: 8e-15  Tdel: 5e-11
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R_minW_pmos 100.
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R_minW_nmos 200.
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# Timing info below.
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ipin_cblock_C 1e-15
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ipin_cblock_Tdel 0.5e-9
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LUT_Tdel 2e-9
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local_mux_Tdel 0.4e-9
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BLE_mux_Tdel 0.2e-9
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Q_to_out_Tdel 0.1e-9
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Tsetup 0.3e-9
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BLE_out_to_local_mux_Tdel 0.1e-9
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ipad_Tdel 3e-9
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opad_Tdel 2e-9