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sim-outorder: SimpleScalar/PISA Tool Set version 3.0 of September, 1998.
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Copyright (c) 1994-1998 by Todd M. Austin.  All Rights Reserved.
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Processor Parameters:
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Issue Width: 4
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Window Size: 16
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Number of Virtual Registers: 32
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Number of Physical Registers: 16
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Datapath Width: 64
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Total Power Consumption: 24.105
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Branch Predictor Power Consumption: 1.14342  (5.17%)
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 branch target buffer power (W): 1.04097
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 local predict power (W): 0.0275244
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 global predict power (W): 0.031332
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 chooser power (W): 0.0206036
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 RAS power (W): 0.0229956
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Rename Logic Power Consumption: 0.0887797  (0.402%)
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 Instruction Decode Power (W): 0.0038821
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 RAT decode_power (W): 0.0273861
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 RAT wordline_power (W): 0.00645964
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 RAT bitline_power (W): 0.0486255
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 DCL Comparators (W): 0.0024263
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Instruction Window Power Consumption: 0.517536  (2.34%)
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 tagdrive (W): 0.0186418
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 tagmatch (W): 0.00697769
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 Selection Logic (W): 0.00331194
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 decode_power (W): 0.0131921
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 wordline_power (W): 0.0176803
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 bitline_power (W): 0.457732
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Load/Store Queue Power Consumption: 0.201758  (0.913%)
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 tagdrive (W): 0.0854673
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 tagmatch (W): 0.0207657
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 decode_power (W): 0.00194105
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 wordline_power (W): 0.00302882
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 bitline_power (W): 0.0905553
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Arch. Register File Power Consumption: 0.769909  (3.48%)
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 decode_power (W): 0.0273861
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 wordline_power (W): 0.0176803
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 bitline_power (W): 0.724843
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Result Bus Power Consumption: 0.499392  (2.26%)
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Total Clock Power: 10.1199  (45.8%)
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Int ALU Power: 1.19732  (5.42%)
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FP ALU Power: 3.66922  (16.6%)
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Instruction Cache Power Consumption: 0.614638  (2.78%)
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 decode_power (W): 0.186809
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 wordline_power (W): 0.00542611
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 bitline_power (W): 0.231588
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 senseamp_power (W): 0.07296
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 tagarray_power (W): 0.117856
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Itlb_power (W): 0.0565504 (0.256%)
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Data Cache Power Consumption: 1.80232  (8.15%)
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 decode_power (W): 0.15387
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 wordline_power (W): 0.0368784
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 bitline_power (W): 0.749615
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 senseamp_power (W): 0.58368
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 tagarray_power (W): 0.278274
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Dtlb_power (W): 0.193103 (0.874%)
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Level 2 Cache Power Consumption: 1.23116 (5.57%)
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 decode_power (W): 0.0990259
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 wordline_power (W): 0.00799512
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 bitline_power (W): 0.83087
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 senseamp_power (W): 0.14592
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 tagarray_power (W): 0.147353
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sim: command line: ./sim-outorder -max:inst 10000000 parser00.O2unroll.gcc.100M.ss 2.1.dict 
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sim: simulation started @ Mon Nov 30 12:19:02 2009, options follow:
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sim-outorder: This simulator implements a very detailed out-of-order issue
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superscalar processor with a two-level memory system and speculative
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execution support.  This simulator is a performance simulator, tracking the
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latency of all pipeline operations.
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# -config                     # load configuration from a file
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# -dumpconfig                 # dump configuration to a file
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# -h                    false # print help message    
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# -v                    false # verbose operation     
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# -d                    false # enable debug message  
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# -i                    false # start in Dlite debugger
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-seed                       1 # random number generator seed (0 for timer seed)
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# -q                    false # initialize and terminate immediately
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# -chkpt               <null> # restore EIO trace execution from <fname>
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# -redir:sim           <null> # redirect simulator output to file (non-interactive only)
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# -redir:prog          <null> # redirect simulated program output to file
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-nice                       0 # simulator scheduling priority
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-max:inst            10000000 # maximum number of inst's to execute
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-fastfwd                    0 # number of insts skipped before timing starts
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# -ptrace              <null> # generate pipetrace, i.e., <fname|stdout|stderr> <range>
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-fetch:ifqsize              4 # instruction fetch queue size (in insts)
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-fetch:mplat                3 # extra branch mis-prediction latency
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-fetch:speed                1 # speed of front-end of machine relative to execution core
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-bpred                  bimod # branch predictor type {nottaken|taken|perfect|bimod|2lev|comb}
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-bpred:bimod     2048 # bimodal predictor config (<table size>)
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-bpred:2lev      1 1024 8 0 # 2-level predictor config (<l1size> <l2size> <hist_size> <xor>)
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-bpred:comb      1024 # combining predictor config (<meta_table_size>)
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-bpred:ras                  8 # return address stack size (0 for no return stack)
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-bpred:btb       512 4 # BTB config (<num_sets> <associativity>)
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# -bpred:spec_update       <null> # speculative predictors update in {ID|WB} (default non-spec)
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-decode:width               4 # instruction decode B/W (insts/cycle)
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-issue:width                4 # instruction issue B/W (insts/cycle)
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-issue:inorder          false # run pipeline with in-order issue
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-issue:wrongpath         true # issue instructions down wrong execution paths
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-commit:width               4 # instruction commit B/W (insts/cycle)
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-ruu:size                  16 # register update unit (RUU) size
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-lsq:size                   8 # load/store queue (LSQ) size
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-cache:dl1       dl1:128:32:4:l # l1 data cache config, i.e., {<config>|none}
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-cache:dl1lat               1 # l1 data cache hit latency (in cycles)
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-cache:dl2       ul2:1024:64:4:l # l2 data cache config, i.e., {<config>|none}
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-cache:dl2lat               6 # l2 data cache hit latency (in cycles)
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-cache:il1       il1:512:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2|none}
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-cache:il1lat               1 # l1 instruction cache hit latency (in cycles)
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-cache:il2                dl2 # l2 instruction cache config, i.e., {<config>|dl2|none}
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-cache:il2lat               6 # l2 instruction cache hit latency (in cycles)
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-cache:flush            false # flush caches on system calls
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-cache:icompress        false # convert 64-bit inst addresses to 32-bit inst equivalents
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-mem:lat         18 2 # memory access latency (<first_chunk> <inter_chunk>)
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-mem:width                  8 # memory access bus width (in bytes)
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-tlb:itlb        itlb:16:4096:4:l # instruction TLB config, i.e., {<config>|none}
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-tlb:dtlb        dtlb:32:4096:4:l # data TLB config, i.e., {<config>|none}
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-tlb:lat                   30 # inst/data TLB miss latency (in cycles)
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-res:ialu                   4 # total number of integer ALU's available
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-res:imult                  1 # total number of integer multiplier/dividers available
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-res:memport                2 # total number of memory system ports available (to CPU)
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-res:fpalu                  4 # total number of floating point ALU's available
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-res:fpmult                 1 # total number of floating point multiplier/dividers available
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# -pcstat              <null> # profile stat(s) against text addr's (mult uses ok)
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-bugcompat              false # operate in backward-compatible bugs mode (for testing only)
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  Pipetrace range arguments are formatted as follows:
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    {{@|#}<start>}:{{@|#|+}<end>}
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  Both ends of the range are optional, if neither are specified, the entire
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  execution is traced.  Ranges that start with a `@' designate an address
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  range to be traced, those that start with an `#' designate a cycle count
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  range.  All other range values represent an instruction count range.  The
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  second argument, if specified with a `+', indicates a value relative
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  to the first argument, e.g., 1000:+100 == 1000:1100.  Program symbols may
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  be used in all contexts.
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    Examples:   -ptrace FOO.trc #0:#1000
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                -ptrace BAR.trc @2000:
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                -ptrace BLAH.trc :1500
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                -ptrace UXXE.trc :
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                -ptrace FOOBAR.trc @main:+278
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  Branch predictor configuration examples for 2-level predictor:
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    Configurations:   N, M, W, X
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      N   # entries in first level (# of shift register(s))
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      W   width of shift register(s)
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      M   # entries in 2nd level (# of counters, or other FSM)
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      X   (yes-1/no-0) xor history and address for 2nd level index
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    Sample predictors:
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      GAg     : 1, W, 2^W, 0
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      GAp     : 1, W, M (M > 2^W), 0
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      PAg     : N, W, 2^W, 0
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      PAp     : N, W, M (M == 2^(N+W)), 0
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      gshare  : 1, W, 2^W, 1
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  Predictor `comb' combines a bimodal and a 2-level predictor.
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  The cache config parameter <config> has the following format:
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    <name>:<nsets>:<bsize>:<assoc>:<repl>
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    <name>   - name of the cache being defined
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    <nsets>  - number of sets in the cache
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    <bsize>  - block size of the cache
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    <assoc>  - associativity of the cache
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    <repl>   - block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random
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    Examples:   -cache:dl1 dl1:4096:32:1:l
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                -dtlb dtlb:128:4096:32:r
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  Cache levels can be unified by pointing a level of the instruction cache
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  hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache
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  configuration arguments.  Most sensible combinations are supported, e.g.,
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    A unified l2 cache (il2 is pointed at dl2):
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      -cache:il1 il1:128:64:1:l -cache:il2 dl2
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      -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
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    Or, a fully unified cache hierarchy (il1 pointed at dl1):
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      -cache:il1 dl1
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      -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
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sim: ** starting performance simulation **
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 Reading the dictionary files: **
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sim: ** simulation statistics **
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sim_num_insn                8446614 # total number of instructions committed
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sim_num_refs                2923489 # total number of loads and stores committed
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sim_num_loads               2009478 # total number of loads committed
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sim_num_stores          914011.0000 # total number of stores committed
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sim_num_branches            2114105 # total number of branches committed
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sim_elapsed_time                  7 # total simulation time in seconds
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sim_inst_rate          1206659.1429 # simulation speed (in insts/sec)
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sim_total_insn             10000002 # total number of instructions executed
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sim_total_refs              3518515 # total number of loads and stores executed
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sim_total_loads             2481827 # total number of loads executed
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sim_total_stores       1036688.0000 # total number of stores executed
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sim_total_branches          2474596 # total number of branches executed
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sim_cycle                   4952396 # total simulation time in cycles
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sim_IPC                      1.7056 # instructions per cycle
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sim_CPI                      0.5863 # cycles per instruction
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sim_exec_BW                  2.0192 # total instructions (mis-spec + committed) per cycle
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sim_IPB                      3.9954 # instruction per branch
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IFQ_count                  14011718 # cumulative IFQ occupancy
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IFQ_fcount                  2874408 # cumulative IFQ full count
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ifq_occupancy                2.8293 # avg IFQ occupancy (insn's)
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ifq_rate                     2.0192 # avg IFQ dispatch rate (insn/cycle)
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ifq_latency                  1.4012 # avg IFQ occupant latency (cycle's)
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ifq_full                     0.5804 # fraction of time (cycle's) IFQ was full
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RUU_count                  52626830 # cumulative RUU occupancy
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RUU_fcount                  1392583 # cumulative RUU full count
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ruu_occupancy               10.6265 # avg RUU occupancy (insn's)
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ruu_rate                     2.0192 # avg RUU dispatch rate (insn/cycle)
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ruu_latency                  5.2627 # avg RUU occupant latency (cycle's)
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ruu_full                     0.2812 # fraction of time (cycle's) RUU was full
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LSQ_count                  19464028 # cumulative LSQ occupancy
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LSQ_fcount                   560741 # cumulative LSQ full count
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lsq_occupancy                3.9302 # avg LSQ occupancy (insn's)
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lsq_rate                     2.0192 # avg LSQ dispatch rate (insn/cycle)
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lsq_latency                  1.9464 # avg LSQ occupant latency (cycle's)
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lsq_full                     0.1132 # fraction of time (cycle's) LSQ was full
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bpred_bimod.lookups         2640851 # total number of bpred lookups
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bpred_bimod.updates         2114103 # total number of updates
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bpred_bimod.addr_hits       1923903 # total number of address-predicted hits
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bpred_bimod.dir_hits        1997025 # total number of direction-predicted hits (includes addr-hits)
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bpred_bimod.misses           117078 # total number of misses
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bpred_bimod.jr_hits          149439 # total number of address-predicted hits for JR's
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bpred_bimod.jr_seen          222191 # total number of JR's seen
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bpred_bimod.jr_non_ras_hits.PP            1 # total number of address-predicted hits for non-RAS JR's
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bpred_bimod.jr_non_ras_seen.PP            2 # total number of non-RAS JR's seen
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bpred_bimod.bpred_addr_rate    0.9100 # branch address-prediction rate (i.e., addr-hits/updates)
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bpred_bimod.bpred_dir_rate    0.9446 # branch direction-prediction rate (i.e., all-hits/updates)
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bpred_bimod.bpred_jr_rate    0.6726 # JR address-prediction rate (i.e., JR addr-hits/JRs seen)
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bpred_bimod.bpred_jr_non_ras_rate.PP    0.5000 # non-RAS JR addr-pred rate (ie, non-RAS JR hits/JRs seen)
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bpred_bimod.retstack_pushes       282397 # total number of address pushed onto ret-addr stack
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bpred_bimod.retstack_pops       306494 # total number of address popped off of ret-addr stack
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bpred_bimod.used_ras.PP       222189 # total number of RAS predictions used
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bpred_bimod.ras_hits.PP       149438 # total number of RAS hits
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bpred_bimod.ras_rate.PP    0.6726 # RAS prediction rate (i.e., RAS hits/used RAS)
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il1.accesses               10635489 # total number of accesses
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il1.hits                   10606480 # total number of hits
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il1.misses                    29009 # total number of misses
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il1.replacements              28542 # total number of replacements
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il1.writebacks                    0 # total number of writebacks
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il1.invalidations                 0 # total number of invalidations
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il1.miss_rate                0.0027 # miss rate (i.e., misses/ref)
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il1.repl_rate                0.0027 # replacement rate (i.e., repls/ref)
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il1.wb_rate                  0.0000 # writeback rate (i.e., wrbks/ref)
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il1.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)
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dl1.accesses                3115851 # total number of accesses
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dl1.hits                    3076419 # total number of hits
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dl1.misses                    39432 # total number of misses
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dl1.replacements              38920 # total number of replacements
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dl1.writebacks                26844 # total number of writebacks
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dl1.invalidations                 0 # total number of invalidations
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dl1.miss_rate                0.0127 # miss rate (i.e., misses/ref)
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dl1.repl_rate                0.0125 # replacement rate (i.e., repls/ref)
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dl1.wb_rate                  0.0086 # writeback rate (i.e., wrbks/ref)
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dl1.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)
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ul2.accesses                  95285 # total number of accesses
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ul2.hits                      81687 # total number of hits
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ul2.misses                    13598 # total number of misses
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ul2.replacements               9502 # total number of replacements
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ul2.writebacks                 8766 # total number of writebacks
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ul2.invalidations                 0 # total number of invalidations
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ul2.miss_rate                0.1427 # miss rate (i.e., misses/ref)
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ul2.repl_rate                0.0997 # replacement rate (i.e., repls/ref)
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ul2.wb_rate                  0.0920 # writeback rate (i.e., wrbks/ref)
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ul2.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)
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itlb.accesses              10635489 # total number of accesses
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itlb.hits                  10635467 # total number of hits
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itlb.misses                      22 # total number of misses
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itlb.replacements                 0 # total number of replacements
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itlb.writebacks                   0 # total number of writebacks
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itlb.invalidations                0 # total number of invalidations
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itlb.miss_rate               0.0000 # miss rate (i.e., misses/ref)
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itlb.repl_rate               0.0000 # replacement rate (i.e., repls/ref)
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itlb.wb_rate                 0.0000 # writeback rate (i.e., wrbks/ref)
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itlb.inv_rate                0.0000 # invalidation rate (i.e., invs/ref)
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dtlb.accesses               3116128 # total number of accesses
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dtlb.hits                   3115994 # total number of hits
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dtlb.misses                     134 # total number of misses
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dtlb.replacements                 8 # total number of replacements
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dtlb.writebacks                   0 # total number of writebacks
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dtlb.invalidations                0 # total number of invalidations
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dtlb.miss_rate               0.0000 # miss rate (i.e., misses/ref)
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dtlb.repl_rate               0.0000 # replacement rate (i.e., repls/ref)
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dtlb.wb_rate                 0.0000 # writeback rate (i.e., wrbks/ref)
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dtlb.inv_rate                0.0000 # invalidation rate (i.e., invs/ref)
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rename_power            439672.4102 # total power usage of rename unit
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bpred_power            5662681.2474 # total power usage of bpred unit
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window_power           2563044.3016 # total power usage of instruction window
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lsq_power               999186.2904 # total power usage of load/store queue
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regfile_power          3812895.9477 # total power usage of arch. regfile
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icache_power           3323991.9540 # total power usage of icache
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dcache_power           9882113.7918 # total power usage of dcache
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dcache2_power          6097210.5863 # total power usage of dcache2
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alu_power              24101029.1273 # total power usage of alu
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falu_power             18171410.8491 # total power usage of falu
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resultbus_power        2473188.9522 # total power usage of resultbus
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clock_power            50117861.8928 # total power usage of clock
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avg_rename_power             0.0888 # avg power usage of rename unit
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avg_bpred_power              1.1434 # avg power usage of bpred unit
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avg_window_power             0.5175 # avg power usage of instruction window
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avg_lsq_power                0.2018 # avg power usage of lsq
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avg_regfile_power            0.7699 # avg power usage of arch. regfile
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avg_icache_power             0.6712 # avg power usage of icache
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avg_dcache_power             1.9954 # avg power usage of dcache
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avg_dcache2_power            1.2312 # avg power usage of dcache2
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avg_alu_power                4.8665 # avg power usage of alu
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avg_falu_power               3.6692 # avg power usage of falu
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avg_resultbus_power          0.4994 # avg power usage of resultbus
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avg_clock_power             10.1199 # avg power usage of clock
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fetch_stage_power      8986673.2014 # total power usage of fetch stage
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dispatch_stage_power    439672.4102 # total power usage of dispatch stage
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issue_stage_power      46115773.0496 # total power usage of issue stage
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avg_fetch_power              1.8146 # average power of fetch unit per cycle
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avg_dispatch_power           0.0888 # average power of dispatch unit per cycle
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avg_issue_power              9.3118 # average power of issue unit per cycle
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total_power            109472876.5017 # total power per cycle
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avg_total_power_cycle       22.1050 # average total power per cycle
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avg_total_power_cycle_nofp_nod2      17.2047 # average total power per cycle
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avg_total_power_insn        10.9473 # average total power per insn
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avg_total_power_insn_nofp_nod2       8.5204 # average total power per insn
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rename_power_cc1        312184.6203 # total power usage of rename unit_cc1
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bpred_power_cc1        2055901.7533 # total power usage of bpred unit_cc1
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window_power_cc1       2063894.6767 # total power usage of instruction window_cc1
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lsq_power_cc1           221162.8829 # total power usage of lsq_cc1
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regfile_power_cc1      2492357.6927 # total power usage of arch. regfile_cc1
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icache_power_cc1       2550135.6106 # total power usage of icache_cc1
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dcache_power_cc1       4335018.6776 # total power usage of dcache_cc1
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dcache2_power_cc1        84222.0675 # total power usage of dcache2_cc1
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alu_power_cc1          4233752.5457 # total power usage of alu_cc1
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resultbus_power_cc1    1731751.3619 # total power usage of resultbus_cc1
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clock_power_cc1        18448252.9224 # total power usage of clock_cc1
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avg_rename_power_cc1         0.0630 # avg power usage of rename unit_cc1
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avg_bpred_power_cc1          0.4151 # avg power usage of bpred unit_cc1
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avg_window_power_cc1         0.4167 # avg power usage of instruction window_cc1
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avg_lsq_power_cc1            0.0447 # avg power usage of lsq_cc1
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avg_regfile_power_cc1        0.5033 # avg power usage of arch. regfile_cc1
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avg_icache_power_cc1         0.5149 # avg power usage of icache_cc1
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avg_dcache_power_cc1         0.8753 # avg power usage of dcache_cc1
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avg_dcache2_power_cc1        0.0170 # avg power usage of dcache2_cc1
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avg_alu_power_cc1            0.8549 # avg power usage of alu_cc1
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avg_resultbus_power_cc1       0.3497 # avg power usage of resultbus_cc1
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avg_clock_power_cc1          3.7251 # avg power usage of clock_cc1
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fetch_stage_power_cc1  4606037.3639 # total power usage of fetch stage_cc1
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dispatch_stage_power_cc1  312184.6203 # total power usage of dispatch stage_cc1
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issue_stage_power_cc1  12669802.2124 # total power usage of issue stage_cc1
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avg_fetch_power_cc1          0.9301 # average power of fetch unit per cycle_cc1
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avg_dispatch_power_cc1       0.0630 # average power of dispatch unit per cycle_cc1
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avg_issue_power_cc1          2.5583 # average power of issue unit per cycle_cc1
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total_power_cycle_cc1  38528634.8118 # total power per cycle_cc1
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avg_total_power_cycle_cc1       7.7798 # average total power per cycle_cc1
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avg_total_power_insn_cc1       3.8529 # average total power per insn_cc1
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rename_power_cc2        221942.7707 # total power usage of rename unit_cc2
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bpred_power_cc2        1208656.5184 # total power usage of bpred unit_cc2
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window_power_cc2       1716359.2420 # total power usage of instruction window_cc2
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lsq_power_cc2           149902.3309 # total power usage of lsq_cc2
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regfile_power_cc2       609026.6220 # total power usage of arch. regfile_cc2
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icache_power_cc2       2550135.6106 # total power usage of icache_cc2
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dcache_power_cc2       3108716.8859 # total power usage of dcache_cc2
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dcache2_power_cc2        58655.7205 # total power usage of dcache2_cc2
369
alu_power_cc2          2598177.7210 # total power usage of alu_cc2
370
resultbus_power_cc2    1090008.0555 # total power usage of resultbus_cc2
371
clock_power_cc2        11964550.5621 # total power usage of clock_cc2
372
avg_rename_power_cc2         0.0448 # avg power usage of rename unit_cc2
373
avg_bpred_power_cc2          0.2441 # avg power usage of bpred unit_cc2
374
avg_window_power_cc2         0.3466 # avg power usage of instruction window_cc2
375
avg_lsq_power_cc2            0.0303 # avg power usage of instruction lsq_cc2
376
avg_regfile_power_cc2        0.1230 # avg power usage of arch. regfile_cc2
377
avg_icache_power_cc2         0.5149 # avg power usage of icache_cc2
378
avg_dcache_power_cc2         0.6277 # avg power usage of dcache_cc2
379
avg_dcache2_power_cc2        0.0118 # avg power usage of dcache2_cc2
380
avg_alu_power_cc2            0.5246 # avg power usage of alu_cc2
381
avg_resultbus_power_cc2       0.2201 # avg power usage of resultbus_cc2
382
avg_clock_power_cc2          2.4159 # avg power usage of clock_cc2
383
fetch_stage_power_cc2  3758792.1290 # total power usage of fetch stage_cc2
384
dispatch_stage_power_cc2  221942.7707 # total power usage of dispatch stage_cc2
385
issue_stage_power_cc2  8721819.9559 # total power usage of issue stage_cc2
386
avg_fetch_power_cc2          0.7590 # average power of fetch unit per cycle_cc2
387
avg_dispatch_power_cc2       0.0448 # average power of dispatch unit per cycle_cc2
388
avg_issue_power_cc2          1.7611 # average power of issue unit per cycle_cc2
389
total_power_cycle_cc2  25276132.0397 # total power per cycle_cc2
390
avg_total_power_cycle_cc2       5.1038 # average total power per cycle_cc2
391
avg_total_power_insn_cc2       2.5276 # average total power per insn_cc2
392
rename_power_cc3        234691.5497 # total power usage of rename unit_cc3
393
bpred_power_cc3        1571063.7228 # total power usage of bpred unit_cc3
394
window_power_cc3       1761577.9964 # total power usage of instruction window_cc3
395
lsq_power_cc3           226148.7738 # total power usage of lsq_cc3
396
regfile_power_cc3       710969.5481 # total power usage of arch. regfile_cc3
397
icache_power_cc3       2627521.2449 # total power usage of icache_cc3
398
dcache_power_cc3       3682368.0286 # total power usage of dcache_cc3
399
dcache2_power_cc3       659957.0962 # total power usage of dcache2_cc3
400
alu_power_cc3          4584905.3789 # total power usage of alu_cc3
401
resultbus_power_cc3    1158699.6307 # total power usage of resultbus_cc3
402
clock_power_cc3        15102228.7704 # total power usage of clock_cc3
403
avg_rename_power_cc3         0.0474 # avg power usage of rename unit_cc3
404
avg_bpred_power_cc3          0.3172 # avg power usage of bpred unit_cc3
405
avg_window_power_cc3         0.3557 # avg power usage of instruction window_cc3
406
avg_lsq_power_cc3            0.0457 # avg power usage of instruction lsq_cc3
407
avg_regfile_power_cc3        0.1436 # avg power usage of arch. regfile_cc3
408
avg_icache_power_cc3         0.5306 # avg power usage of icache_cc3
409
avg_dcache_power_cc3         0.7436 # avg power usage of dcache_cc3
410
avg_dcache2_power_cc3        0.1333 # avg power usage of dcache2_cc3
411
avg_alu_power_cc3            0.9258 # avg power usage of alu_cc3
412
avg_resultbus_power_cc3       0.2340 # avg power usage of resultbus_cc3
413
avg_clock_power_cc3          3.0495 # avg power usage of clock_cc3
414
fetch_stage_power_cc3  4198584.9678 # total power usage of fetch stage_cc3
415
dispatch_stage_power_cc3  234691.5497 # total power usage of dispatch stage_cc3
416
issue_stage_power_cc3  12073656.9046 # total power usage of issue stage_cc3
417
avg_fetch_power_cc3          0.8478 # average power of fetch unit per cycle_cc3
418
avg_dispatch_power_cc3       0.0474 # average power of dispatch unit per cycle_cc3
419
avg_issue_power_cc3          2.4379 # average power of issue unit per cycle_cc3
420
total_power_cycle_cc3  32320131.7405 # total power per cycle_cc3
421
avg_total_power_cycle_cc3       6.5262 # average total power per cycle_cc3
422
avg_total_power_insn_cc3       3.2320 # average total power per insn_cc3
423
total_rename_access         9999704 # total number accesses of rename unit
424
total_bpred_access          2114103 # total number accesses of bpred unit
425
total_window_access        33799702 # total number accesses of instruction window
426
total_lsq_access            3129757 # total number accesses of load/store queue
427
total_regfile_access       10785974 # total number accesses of arch. regfile
428
total_icache_access        10635814 # total number accesses of icache
429
total_dcache_access         3115851 # total number accesses of dcache
430
total_dcache2_access          95285 # total number accesses of dcache2
431
total_alu_access            8679955 # total number accesses of alu
432
total_resultbus_access      8980590 # total number accesses of resultbus
433
avg_rename_access            2.0192 # avg number accesses of rename unit
434
avg_bpred_access             0.4269 # avg number accesses of bpred unit
435
avg_window_access            6.8249 # avg number accesses of instruction window
436
avg_lsq_access               0.6320 # avg number accesses of lsq
437
avg_regfile_access           2.1779 # avg number accesses of arch. regfile
438
avg_icache_access            2.1476 # avg number accesses of icache
439
avg_dcache_access            0.6292 # avg number accesses of dcache
440
avg_dcache2_access           0.0192 # avg number accesses of dcache2
441
avg_alu_access               1.7527 # avg number accesses of alu
442
avg_resultbus_access         1.8134 # avg number accesses of resultbus
443
max_rename_access                 4 # max number accesses of rename unit
444
max_bpred_access                  3 # max number accesses of bpred unit
445
max_window_access                16 # max number accesses of instruction window
446
max_lsq_access                    4 # max number accesses of load/store queue
447
max_regfile_access               12 # max number accesses of arch. regfile
448
max_icache_access                 4 # max number accesses of icache
449
max_dcache_access                 4 # max number accesses of dcache
450
max_dcache2_access                4 # max number accesses of dcache2
451
max_alu_access                    4 # max number accesses of alu
452
max_resultbus_access              8 # max number accesses of resultbus
453
max_cycle_power_cc1         13.1371 # maximum cycle power usage of cc1
454
max_cycle_power_cc2          9.8054 # maximum cycle power usage of cc2
455
max_cycle_power_cc3         10.7910 # maximum cycle power usage of cc3
456
parasitic_power_cc1    3306123.7274 # parasitic power cc1
457
parasitic_power_cc2    3306123.7274 # parasitic power cc2
458
parasitic_power_cc3    3306123.7274 # parasitic power cc3
459
min amperage                 0.0000 # min amperage
460
max amperage                 5.6795 # max amperage
461
slow_cycles                  0.0000 # slow cycles
462
fast_cycles                  0.0000 # fast cycles
463
sim_invalid_addrs                 0 # total non-speculative bogus addresses seen (debug var)
464
ld_text_base             0x00400000 # program text (code) segment base
465
ld_text_size                 278720 # program text (code) size in bytes
466
ld_data_base             0x10000000 # program initialized data segment base
467
ld_data_size                 200880 # program init'ed `.data' and uninit'ed `.bss' size in bytes
468
ld_stack_base            0x7fffc000 # program stack segment base (highest address in stack)
469
ld_stack_size                 16384 # program initial stack size
470
ld_prog_entry            0x00400140 # program entry point (initial PC)
471
ld_environ_base          0x7fff8000 # program environment base address address
472
ld_target_big_endian              0 # target executable endian-ness, non-zero if big endian
473
mem.page_count                  204 # total number of pages allocated
474
mem.page_mem                   816k # total size of memory pages allocated
475
mem.ptab_misses                 235 # total first level page table misses
476
mem.ptab_accesses          29002893 # total page table accesses
477
mem.ptab_miss_rate           0.0000 # first level page table miss rate
478

    
479

    
480
Cache Parameters:
481
  Size in bytes: 16384
482
  Number of sets: 512
483
  Associativity: 4
484
  Block Size (bytes): 8
485

    
486
Access Time: 9.27925e-09
487
Cycle Time:  1.09081e-08
488

    
489
Best Ndwl (L1): 8
490
Best Ndbl (L1): 1
491
Best Nspd (L1): 1
492
Best Ntwl (L1): 1
493
Best Ntbl (L1): 4
494
Best Ntspd (L1): 1
495

    
496
Time Components:
497
 data side (with Output driver) (ns): 8.44162
498
 tag side (ns): 8.55667
499
 decode_data (ns): 5.29318
500
 wordline_data (ns): 1.03507
501
 bitline_data (ns): 0.810785
502
 sense_amp_data (ns): 0.58
503
 decode_tag (ns): 2.37065
504
 wordline_tag (ns): 1.36749
505
 bitline_tag (ns): 0.158246
506
 sense_amp_tag (ns): 0.26
507
 compare (ns): 2.42991
508
 mux driver (ns): 1.6125
509
 sel inverter (ns): 0.357877
510
 data output driver (ns): 0.722579
511
 total data path (with output driver) (ns): 7.71904
512
 total tag path is set assoc (ns): 8.55667
513
 precharge time (ns): 1.6289
514

    
515
Cache Parameters:
516
  Size in bytes: 16384
517
  Number of sets: 512
518
  Associativity: 1
519
  Block Size (bytes): 32
520

    
521
Access Time: 6.07496e-09
522
Cycle Time:  7.99836e-09
523

    
524
Best Ndwl (L1): 2
525
Best Ndbl (L1): 2
526
Best Nspd (L1): 1
527
Best Ntwl (L1): 1
528
Best Ntbl (L1): 2
529
Best Ntspd (L1): 2
530

    
531
Time Components:
532
 data side (with Output driver) (ns): 6.07496
533
 tag side (ns): 6.05737
534
 decode_data (ns): 2.92313
535
 wordline_data (ns): 1.32956
536
 bitline_data (ns): 0.452976
537
 sense_amp_data (ns): 0.58
538
 decode_tag (ns): 1.84499
539
 wordline_tag (ns): 0.825016
540
 bitline_tag (ns): 0.252886
541
 sense_amp_tag (ns): 0.26
542
 compare (ns): 2.30022
543
 valid signal driver (ns): 0.574251
544
 data output driver (ns): 0.789293
545
 total data path (with output driver) (ns): 5.28567
546
 total tag path is dm (ns): 6.05737
547
 precharge time (ns): 1.92339
548

    
549
Cache Parameters:
550
  Size in bytes: 16384
551
  Number of sets: 128
552
  Associativity: 4
553
  Block Size (bytes): 32
554

    
555
Access Time: 9.14093e-09
556
Cycle Time:  1.11718e-08
557

    
558
Best Ndwl (L1): 4
559
Best Ndbl (L1): 2
560
Best Nspd (L1): 1
561
Best Ntwl (L1): 1
562
Best Ntbl (L1): 2
563
Best Ntspd (L1): 1
564

    
565
Time Components:
566
 data side (with Output driver) (ns): 6.05114
567
 tag side (ns): 7.98848
568
 decode_data (ns): 2.92572
569
 wordline_data (ns): 1.437
570
 bitline_data (ns): -0.0440331
571
 sense_amp_data (ns): 0.58
572
 decode_tag (ns): 1.46851
573
 wordline_tag (ns): 1.27791
574
 bitline_tag (ns): -0.0315811
575
 sense_amp_tag (ns): 0.26
576
 compare (ns): 2.29478
577
 mux driver (ns): 2.37376
578
 sel inverter (ns): 0.345094
579
 data output driver (ns): 1.15245
580
 total data path (with output driver) (ns): 4.89869
581
 total tag path is set assoc (ns): 7.98848
582
 precharge time (ns): 2.03083
583

    
584
Cache Parameters:
585
  Size in bytes: 262144
586
  Number of sets: 1024
587
  Associativity: 4
588
  Block Size (bytes): 64
589

    
590
Access Time: 1.44948e-08
591
Cycle Time:  1.76863e-08
592

    
593
Best Ndwl (L1): 2
594
Best Ndbl (L1): 2
595
Best Nspd (L1): 1
596
Best Ntwl (L1): 1
597
Best Ntbl (L1): 4
598
Best Ntspd (L1): 1
599

    
600
Time Components:
601
 data side (with Output driver) (ns): 11.3269
602
 tag side (ns): 12.2049
603
 decode_data (ns): 4.99158
604
 wordline_data (ns): 2.59771
605
 bitline_data (ns): 0.867749
606
 sense_amp_data (ns): 0.58
607
 decode_tag (ns): 4.52586
608
 wordline_tag (ns): 1.24192
609
 bitline_tag (ns): 0.46158
610
 sense_amp_tag (ns): 0.26
611
 compare (ns): 2.17054
612
 mux driver (ns): 3.21212
613
 sel inverter (ns): 0.332908
614
 data output driver (ns): 2.28987
615
 total data path (with output driver) (ns): 9.03704
616
 total tag path is set assoc (ns): 12.2049
617
 precharge time (ns): 3.19154