Revision db11713d
Fixed timing in current sensing
The ADC interrupt didn't clear the TIFR timer interrupt flag, which
means the ADC wasn't triggered again on the next compare match.
| toolbox/current.c | ||
|---|---|---|
| 20 | 20 |
/* |
| 21 | 21 |
* COM1A = COM1B = 0, disconnect pins |
| 22 | 22 |
* WGM1 = 4, clear timer on compare A |
| 23 |
* CS1 = 5, 1024 prescaler
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|
| 23 |
* CS1 = 1, no prescaler
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|
| 24 | 24 |
*/ |
| 25 |
TCCR1B |= _BV(WGM12) | _BV(CS12) | _BV(CS10);
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|
| 25 |
TCCR1B = _BV(WGM12) | _BV(CS10);
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|
| 26 | 26 |
|
| 27 | 27 |
/* Timer is cleared on A, ADC is triggered on B */ |
| 28 |
OCR1A = F_CPU / 1024 / SAMPLES_PER_CYCLE / CYCLES_PER_SECOND;
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| 29 |
OCR1B = 0;
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| 28 |
OCR1A = F_CPU / SAMPLES_PER_CYCLE / CYCLES_PER_SECOND; |
|
| 29 |
OCR1B = OCR1A;
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|
| 30 | 30 |
|
| 31 | 31 |
/* |
| 32 | 32 |
* REFS = 0, Vcc reference (set to 2 for internal 1.1V reference) |
| 33 | 33 |
* MUX = 8, PB3(ADC8) |
| 34 | 34 |
*/ |
| 35 | 35 |
ADMUX = _BV(MUX3); |
| 36 |
DIDR1 |= _BV(ADC8D); |
|
| 36 | 37 |
|
| 37 | 38 |
/* |
| 38 | 39 |
* ADLAR = 0, right adjust result |
| ... | ... | |
| 45 | 46 |
* ADSC = 0, don't start yet |
| 46 | 47 |
* ADATE = 1, auto trigger |
| 47 | 48 |
* ADIE = 1, enable interrupt |
| 48 |
* ADPS = 4, prescale clock by 16
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|
| 49 |
* ADPS = 6, prescale clock by 64
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|
| 49 | 50 |
*/ |
| 50 |
ADCSRA |= _BV(ADEN) | _BV(ADATE) | _BV(ADIE) | _BV(ADPS2);
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| 51 |
ADCSRA = _BV(ADEN) | _BV(ADATE) | _BV(ADIE) | _BV(ADPS2) | _BV(ADPS1);
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| 51 | 52 |
} |
| 52 | 53 |
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| 53 | 54 |
ISR(ADC_vect) {
|
| 54 | 55 |
unsigned int old, new; |
| 55 | 56 |
|
| 57 |
/* clear the timer interrupt flag so that the ADC will be triggered again |
|
| 58 |
* next time the timer resets */ |
|
| 59 |
TIFR |= _BV(OCF1B); |
|
| 60 |
|
|
| 56 | 61 |
new = ADC; |
| 57 | 62 |
|
| 58 | 63 |
/* put sample into ring buffer */ |
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