root / scout_gumstix / u-boot-scout.patch @ 54f7fa50
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| 1 | 3aec4aa2 | Tom Mullins | diff -rupN u-boot-2012.07.orig/board/overo/overo.h u-boot-2012.07/board/overo/overo.h
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| 2 | --- u-boot-2012.07.orig/board/overo/overo.h 2012-12-08 20:32:40.707945524 -0500
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| 3 | +++ u-boot-2012.07/board/overo/overo.h 2012-12-08 21:03:39.231867005 -0500
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| 4 | @@ -136,34 +136,34 @@ const omap3_sysinfo sysinfo = { |
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| 5 | /* - SMSC911X_NRES*/\ |
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| 6 | MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | DIS | M4)) /*GPIO_65*/\ |
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| 7 | /*DSS*/\ |
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| 8 | - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
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| 9 | - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
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| 10 | - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
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| 11 | - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
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| 12 | - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
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| 13 | - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
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| 14 | - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
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| 15 | - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
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| 16 | - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
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| 17 | - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
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| 18 | - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
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| 19 | - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
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| 20 | - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
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| 21 | - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
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| 22 | - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
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| 23 | - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
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| 24 | - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
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| 25 | - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
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| 26 | - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
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| 27 | - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
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| 28 | - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
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| 29 | - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
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| 30 | - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
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| 31 | - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
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| 32 | - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
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| 33 | - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
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| 34 | - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
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| 35 | - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
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| 36 | + MUX_VAL(CP(DSS_PCLK), (IEN | PTD | DIS | M4)) /*GPIO_66*/\
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| 37 | + MUX_VAL(CP(DSS_HSYNC), (IEN | PTD | DIS | M4)) /*GPIO_67*/\
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| 38 | + MUX_VAL(CP(DSS_VSYNC), (IEN | PTD | DIS | M4)) /*GPIO_68*/\
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| 39 | + MUX_VAL(CP(DSS_ACBIAS), (IEN | PTD | DIS | M4)) /*GPIO_69*/\
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| 40 | + MUX_VAL(CP(DSS_DATA0), (IEN | PTD | DIS | M4)) /*GPIO_70*/\
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| 41 | + MUX_VAL(CP(DSS_DATA1), (IEN | PTD | DIS | M4)) /*GPIO_71*/\
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| 42 | + MUX_VAL(CP(DSS_DATA2), (IEN | PTD | DIS | M4)) /*GPIO_72*/\
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| 43 | + MUX_VAL(CP(DSS_DATA3), (IEN | PTD | DIS | M4)) /*GPIO_73*/\
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| 44 | + MUX_VAL(CP(DSS_DATA4), (IEN | PTD | DIS | M4)) /*GPIO_74*/\
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| 45 | + MUX_VAL(CP(DSS_DATA5), (IEN | PTD | DIS | M4)) /*GPIO_75*/\
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| 46 | + MUX_VAL(CP(DSS_DATA6), (IEN | PTD | DIS | M4)) /*GPIO_76*/\
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| 47 | + MUX_VAL(CP(DSS_DATA7), (IEN | PTD | DIS | M4)) /*GPIO_77*/\
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| 48 | + MUX_VAL(CP(DSS_DATA8), (IEN | PTD | DIS | M4)) /*GPIO_78*/\
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| 49 | + MUX_VAL(CP(DSS_DATA9), (IEN | PTD | DIS | M4)) /*GPIO_79*/\
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| 50 | + MUX_VAL(CP(DSS_DATA10), (IEN | PTD | DIS | M4)) /*GPIO_80*/\
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| 51 | + MUX_VAL(CP(DSS_DATA11), (IEN | PTD | DIS | M4)) /*GPIO_81*/\
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| 52 | + MUX_VAL(CP(DSS_DATA12), (IEN | PTD | DIS | M4)) /*GPIO_82*/\
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| 53 | + MUX_VAL(CP(DSS_DATA13), (IEN | PTD | DIS | M4)) /*GPIO_83*/\
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| 54 | + MUX_VAL(CP(DSS_DATA14), (IEN | PTD | DIS | M4)) /*GPIO_84*/\
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| 55 | + MUX_VAL(CP(DSS_DATA15), (IEN | PTD | DIS | M4)) /*GPIO_85*/\
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| 56 | + MUX_VAL(CP(DSS_DATA16), (IEN | PTD | DIS | M4)) /*GPIO_86*/\
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| 57 | + MUX_VAL(CP(DSS_DATA17), (IEN | PTD | DIS | M4)) /*GPIO_87*/\
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| 58 | + MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\
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| 59 | + MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\
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| 60 | + MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\
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| 61 | + MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\
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| 62 | + MUX_VAL(CP(DSS_DATA22), (IEN | PTD | DIS | M4)) /*GPIO_92*/\
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| 63 | + MUX_VAL(CP(DSS_DATA23), (IEN | PTD | DIS | M4)) /*GPIO_93*/\
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| 64 | /*CAMERA*/\ |
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| 65 | MUX_VAL(CP(CAM_HS), (IEN | PTU | DIS | M0)) /*CAM_HS */\ |
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| 66 | MUX_VAL(CP(CAM_VS), (IEN | PTU | DIS | M0)) /*CAM_VS */\ |
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| 67 | @@ -222,10 +222,10 @@ const omap3_sysinfo sysinfo = { |
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| 68 | MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\ |
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| 69 | MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\ |
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| 70 | MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\ |
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| 71 | - MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\
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| 72 | - MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
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| 73 | - MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
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| 74 | - MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
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| 75 | + MUX_VAL(CP(UART2_CTS), (IDIS | PTD | DIS | M2)) /*GPT9_PWM_EVT*/\
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| 76 | + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M2)) /*GPT10_PWM_EVT*/\
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| 77 | + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M2)) /*GPT11_PWM_EVT*/\
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| 78 | + MUX_VAL(CP(UART2_RX), (IDIS | PTD | DIS | M2)) /*GPT8_PWM_EVT*/\
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| 79 | MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ |
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| 80 | MUX_VAL(CP(UART1_RTS), (IEN | PTU | DIS | M4)) /*GPIO_149*/ \ |
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| 81 | MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\ |