root / prex-0.9.0 / bsp / hal / arm / integrator / clock.c @ 03e9c04a
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/*-
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* Copyright (c) 2008, Kohsuke Ohtani
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* clock.c - clock driver
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*/
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#include <kernel.h> |
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#include <timer.h> |
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#include <irq.h> |
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#include <cpufunc.h> |
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#include <sys/ipl.h> |
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#include "platform.h" |
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/* Interrupt vector for timer (TMR1) */
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#define CLOCK_IRQ 6 |
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/* The clock rate per second - 1Mhz */
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#define CLOCK_RATE 1000000L |
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/* The initial counter value */
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#define TIMER_COUNT (CLOCK_RATE / HZ)
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/* Timer 1 registers */
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#define TMR_LOAD (*(volatile uint32_t *)(TIMER_BASE + 0x100)) |
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#define TMR_VAL (*(volatile uint32_t *)(TIMER_BASE + 0x104)) |
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#define TMR_CTRL (*(volatile uint32_t *)(TIMER_BASE + 0x108)) |
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#define TMR_CLR (*(volatile uint32_t *)(TIMER_BASE + 0x10c)) |
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/* Timer control register */
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#define TCTRL_DISABLE 0x00 |
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#define TCTRL_ENABLE 0x80 |
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#define TCTRL_PERIODIC 0x40 |
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#define TCTRL_INTEN 0x20 |
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#define TCTRL_SCALE256 0x08 |
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#define TCTRL_SCALE16 0x04 |
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#define TCTRL_32BIT 0x02 |
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#define TCTRL_ONESHOT 0x01 |
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/*
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* Clock interrupt service routine.
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* No H/W reprogram is required.
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*/
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static int |
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clock_isr(void *arg)
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{ |
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splhigh(); |
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timer_handler(); |
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TMR_CLR = 0x01; /* Clear timer interrupt */ |
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spl0(); |
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return INT_DONE;
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} |
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/*
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* Initialize clock H/W chip.
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* Setup clock tick rate and install clock ISR.
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*/
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void
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clock_init(void)
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{ |
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irq_t clock_irq; |
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/* Setup counter value */
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TMR_CTRL = TCTRL_DISABLE; |
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TMR_LOAD = TIMER_COUNT; |
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TMR_CTRL |= (TCTRL_ENABLE | TCTRL_PERIODIC); |
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/* Install ISR */
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clock_irq = irq_attach(CLOCK_IRQ, IPL_CLOCK, 0, &clock_isr,
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IST_NONE, NULL);
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/* Enable timer interrupt */
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TMR_CTRL |= TCTRL_INTEN; |
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DPRINTF(("Clock rate: %d ticks/sec\n", CONFIG_HZ));
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} |