root / prex-0.9.0 / bsp / hal / x86 / arch / cpu.c @ 03e9c04a
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1 | 03e9c04a | Brad Neuman | /*-
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2 | * Copyright (c) 2005-2007, Kohsuke Ohtani
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3 | * All rights reserved.
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4 | *
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5 | * Redistribution and use in source and binary forms, with or without
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6 | * modification, are permitted provided that the following conditions
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7 | * are met:
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8 | * 1. Redistributions of source code must retain the above copyright
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9 | * notice, this list of conditions and the following disclaimer.
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10 | * 2. Redistributions in binary form must reproduce the above copyright
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11 | * notice, this list of conditions and the following disclaimer in the
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12 | * documentation and/or other materials provided with the distribution.
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13 | * 3. Neither the name of the author nor the names of any co-contributors
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14 | * may be used to endorse or promote products derived from this software
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15 | * without specific prior written permission.
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16 | *
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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27 | * SUCH DAMAGE.
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28 | */
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29 | |||
30 | /*
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31 | * cpu.c - cpu dependent routines for Intel x86
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32 | */
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33 | |||
34 | #include <machine/syspage.h> |
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35 | #include <kernel.h> |
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36 | #include <cpu.h> |
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37 | #include <locore.h> |
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38 | #include <cpufunc.h> |
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39 | |||
40 | typedef void (*trapfn_t)(void); |
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41 | |||
42 | /*
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43 | * Descriptors
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44 | */
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45 | static struct seg_desc gdt[NGDTS]; |
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46 | static struct gate_desc idt[NIDTS]; |
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47 | static struct tss tss; |
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48 | |||
49 | /*
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50 | * Interrupt table
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51 | */
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52 | static const trapfn_t intr_table[] = { |
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53 | intr_0, intr_1, intr_2, intr_3, intr_4, intr_5, intr_6, |
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54 | intr_7, intr_8, intr_9, intr_10, intr_11, intr_12, intr_13, |
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55 | intr_14, intr_15 |
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56 | }; |
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57 | |||
58 | /*
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59 | * Trap table
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60 | */
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61 | static const trapfn_t trap_table[] = { |
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62 | trap_0, trap_1, trap_2, trap_3, trap_4, trap_5, trap_6, |
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63 | trap_7, trap_8, trap_9, trap_10, trap_11, trap_12, trap_13, |
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64 | trap_14, trap_15, trap_16, trap_17, trap_18 |
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65 | }; |
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66 | #define NTRAPS (int)(sizeof(trap_table) / sizeof(void *)) |
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67 | |||
68 | /*
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69 | * Set kernel stack pointer in TSS (task state segment).
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70 | * An actual value of the register is automatically set when
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71 | * CPU enters kernel mode next time.
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72 | */
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73 | void
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74 | tss_set(uint32_t kstack) |
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75 | { |
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76 | |||
77 | tss.esp0 = kstack; |
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78 | } |
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79 | |||
80 | /*
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81 | * tss_get() returns current esp0 value for trap handler.
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82 | */
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83 | uint32_t |
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84 | tss_get(void)
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85 | { |
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86 | |||
87 | return tss.esp0;
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88 | } |
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89 | |||
90 | /*
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91 | * Set GDT (global descriptor table) members into specified vector
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92 | */
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93 | static void |
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94 | gdt_set(int vec, void *base, size_t limit, int type, u_int size) |
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95 | { |
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96 | struct seg_desc *seg = &gdt[vec];
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97 | |||
98 | if (limit > 0xfffff) { |
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99 | limit >>= 12;
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100 | size |= SIZE_4K; |
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101 | } |
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102 | seg->limit_lo = limit; |
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103 | seg->base_lo = (u_int)base & 0xffff;
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104 | seg->base_mid = ((u_int)base >> 16) & 0xff; |
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105 | seg->limit_hi = limit >> 16;
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106 | seg->base_hi = (u_int)base >> 24;
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107 | seg->type = (u_int)type | ST_PRESENT; |
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108 | seg->size = size; |
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109 | } |
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110 | |||
111 | /*
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112 | * Set IDT (interrupt descriptor table) members into specified vector
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113 | */
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114 | static void |
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115 | idt_set(int vec, trapfn_t off, u_int sel, int type) |
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116 | { |
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117 | struct gate_desc *gate = &idt[vec];
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118 | |||
119 | gate->offset_lo = (u_int)off & 0xffff;
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120 | gate->selector = sel; |
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121 | gate->nr_copy = 0;
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122 | gate->type = (u_int)type | ST_PRESENT; |
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123 | gate->offset_hi = (u_int)off >> 16;
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124 | } |
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125 | |||
126 | /*
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127 | * Setup the GDT and load it.
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128 | */
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129 | static void |
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130 | gdt_init(void)
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131 | { |
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132 | struct desc_p gdt_p;
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133 | |||
134 | /* Set system vectors */
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135 | gdt_set(KERNEL_CS / 8, 0, 0xffffffff, ST_KERN | ST_CODE_R, SIZE_32); |
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136 | gdt_set(KERNEL_DS / 8, 0, 0xffffffff, ST_KERN | ST_DATA_W, SIZE_32); |
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137 | gdt_set(USER_CS / 8, 0, 0xffffffff, ST_USER | ST_CODE_R, SIZE_32); |
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138 | gdt_set(USER_DS / 8, 0, 0xffffffff, ST_USER | ST_DATA_W, SIZE_32); |
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139 | |||
140 | /* Clear TSS Busy */
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141 | gdt[KERNEL_TSS / 8].type &= ~ST_TSS_BUSY;
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142 | |||
143 | /* Load GDT */
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144 | gdt_p.limit = (uint16_t)(sizeof(gdt) - 1); |
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145 | gdt_p.base = (uint32_t)&gdt; |
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146 | load_gdt(&gdt_p); |
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147 | } |
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148 | |||
149 | /*
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150 | * Setup the interrupt descriptor table and load it.
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151 | *
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152 | * IDT layout:
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153 | * 0x00 - 0x12 ... S/W trap
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154 | * 0x13 - 0x1f ... Intel reserved
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155 | * 0x20 - 0x3f ... H/W interrupt
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156 | * 0x40 ... System call trap
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157 | */
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158 | static void |
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159 | idt_init(void)
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160 | { |
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161 | struct desc_p idt_p;
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162 | int i;
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163 | |||
164 | /* Fill all vectors with default handler */
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165 | for (i = 0; i < NIDTS; i++) |
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166 | idt_set(i, trap_default, KERNEL_CS, ST_KERN | ST_TRAP_GATE); |
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167 | |||
168 | /* Setup trap handlers */
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169 | for (i = 0; i < NTRAPS; i++) |
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170 | idt_set(i, trap_table[i], KERNEL_CS, ST_KERN | ST_TRAP_GATE); |
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171 | |||
172 | /* Setup interrupt handlers */
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173 | for (i = 0; i < 16; i++) |
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174 | idt_set(0x20 + i, intr_table[i], KERNEL_CS,
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175 | ST_KERN | ST_INTR_GATE); |
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176 | |||
177 | /* Setup debug trap */
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178 | idt_set(3, trap_3, KERNEL_CS, ST_USER | ST_TRAP_GATE);
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179 | |||
180 | /* Setup system call handler */
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181 | idt_set(SYSCALL_INT, syscall_entry, KERNEL_CS, |
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182 | ST_USER | ST_TRAP_GATE); |
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183 | |||
184 | /* Load IDT */
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185 | idt_p.limit = (uint16_t)(sizeof(idt) - 1); |
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186 | idt_p.base = (uint32_t)&idt; |
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187 | load_idt(&idt_p); |
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188 | } |
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189 | |||
190 | /*
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191 | * Initialize the task state segment.
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192 | * Only one static TSS is used for all contexts.
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193 | */
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194 | static void |
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195 | tss_init(void)
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196 | { |
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197 | |||
198 | gdt_set(KERNEL_TSS / 8, &tss, sizeof(struct tss) - 1, |
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199 | ST_KERN | ST_TSS, 0);
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200 | /* Setup TSS */
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201 | memset(&tss, 0, sizeof(struct tss)); |
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202 | tss.ss0 = KERNEL_DS; |
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203 | tss.esp0 = (uint32_t)BOOTSTKTOP; |
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204 | tss.cs = (uint32_t)USER_CS | 3;
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205 | tss.ds = tss.es = tss.ss = tss.fs = tss.gs = (uint32_t)USER_CS | 3;
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206 | tss.io_bitmap_offset = INVALID_IO_BITMAP; |
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207 | load_tr(KERNEL_TSS); |
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208 | } |
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209 | |||
210 | /*
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211 | * Initialize CPU state.
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212 | * Setup segment and interrupt descriptor.
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213 | */
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214 | void
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215 | cpu_init(void)
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216 | { |
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217 | |||
218 | /*
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219 | * Initialize descriptors.
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220 | * Setup segment and interrupt descriptor.
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221 | */
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222 | gdt_init(); |
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223 | idt_init(); |
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224 | tss_init(); |
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225 | } |