root / prex-0.9.0 / bsp / hal / arm / integrator / interrupt.c @ 03e9c04a
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1 | 03e9c04a | Brad Neuman | /*-
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2 | * Copyright (c) 2008, Kohsuke Ohtani
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3 | * All rights reserved.
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4 | *
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5 | * Redistribution and use in source and binary forms, with or without
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6 | * modification, are permitted provided that the following conditions
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7 | * are met:
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8 | * 1. Redistributions of source code must retain the above copyright
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9 | * notice, this list of conditions and the following disclaimer.
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10 | * 2. Redistributions in binary form must reproduce the above copyright
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11 | * notice, this list of conditions and the following disclaimer in the
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12 | * documentation and/or other materials provided with the distribution.
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13 | * 3. Neither the name of the author nor the names of any co-contributors
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14 | * may be used to endorse or promote products derived from this software
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15 | * without specific prior written permission.
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16 | *
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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27 | * SUCH DAMAGE.
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28 | */
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29 | |||
30 | /*
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31 | * interrupt.c - interrupt handling routines
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32 | */
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33 | |||
34 | #include <sys/ipl.h> |
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35 | #include <kernel.h> |
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36 | #include <hal.h> |
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37 | #include <irq.h> |
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38 | #include <cpufunc.h> |
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39 | #include <context.h> |
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40 | #include <locore.h> |
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41 | |||
42 | #include "platform.h" |
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43 | |||
44 | /* Number of IRQ lines */
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45 | #define NIRQS 29 |
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46 | |||
47 | /* Registers for interrupt control unit - enable/flag/master */
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48 | #define ICU_IRQSTS (*(volatile uint32_t *)(ICU_BASE + 0x00)) |
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49 | #define ICU_IRQEN (*(volatile uint32_t *)(ICU_BASE + 0x08)) |
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50 | #define ICU_IRQENSET (*(volatile uint32_t *)(ICU_BASE + 0x08)) |
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51 | #define ICU_IRQENCLR (*(volatile uint32_t *)(ICU_BASE + 0x0C)) |
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52 | |||
53 | /*
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54 | * Interrupt Priority Level
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55 | *
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56 | * Each interrupt has its logical priority level, with 0 being
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57 | * the lowest priority. While some ISR is running, all lower
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58 | * priority interrupts are masked off.
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59 | */
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60 | volatile int irq_level; |
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61 | |||
62 | /*
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63 | * Interrupt mapping table
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64 | */
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65 | static int ipl_table[NIRQS]; /* vector -> level */ |
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66 | static uint32_t mask_table[NIPLS]; /* level -> mask */ |
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67 | |||
68 | /*
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69 | * Set mask for current ipl
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70 | */
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71 | static void |
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72 | update_mask(void)
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73 | { |
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74 | u_int mask = mask_table[irq_level]; |
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75 | |||
76 | ICU_IRQENCLR = ~mask; |
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77 | ICU_IRQENSET = mask; |
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78 | } |
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79 | |||
80 | /*
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81 | * Unmask interrupt in ICU for specified irq.
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82 | * The interrupt mask table is also updated.
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83 | * Assumes CPU interrupt is disabled in caller.
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84 | */
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85 | void
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86 | interrupt_unmask(int vector, int level) |
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87 | { |
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88 | int i;
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89 | uint32_t unmask = (uint32_t)1 << vector;
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90 | |||
91 | /* Save level mapping */
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92 | ipl_table[vector] = level; |
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93 | |||
94 | /*
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95 | * Unmask the target interrupt for all
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96 | * lower interrupt levels.
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97 | */
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98 | for (i = 0; i < level; i++) |
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99 | mask_table[i] |= unmask; |
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100 | update_mask(); |
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101 | } |
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102 | |||
103 | /*
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104 | * Mask interrupt in ICU for specified irq.
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105 | * Interrupt must be disabled when this routine is called.
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106 | */
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107 | void
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108 | interrupt_mask(int vector)
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109 | { |
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110 | int i, level;
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111 | u_int mask = (uint16_t)~(1 << vector);
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112 | |||
113 | level = ipl_table[vector]; |
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114 | for (i = 0; i < level; i++) |
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115 | mask_table[i] &= mask; |
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116 | ipl_table[vector] = IPL_NONE; |
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117 | update_mask(); |
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118 | } |
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119 | |||
120 | /*
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121 | * Setup interrupt mode.
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122 | * Select whether an interrupt trigger is edge or level.
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123 | */
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124 | void
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125 | interrupt_setup(int vector, int mode) |
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126 | { |
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127 | /* nop */
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128 | } |
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129 | |||
130 | /*
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131 | * Common interrupt handler.
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132 | */
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133 | void
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134 | interrupt_handler(void)
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135 | { |
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136 | uint32_t bits; |
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137 | int vector, old_ipl, new_ipl;
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138 | |||
139 | /* Get interrupt source */
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140 | bits = ICU_IRQSTS; |
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141 | for (vector = 0; vector < NIRQS; vector++) { |
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142 | if (bits & (uint32_t)(1 << vector)) |
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143 | break;
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144 | } |
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145 | if (vector == NIRQS)
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146 | goto out;
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147 | |||
148 | /* Adjust interrupt level */
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149 | old_ipl = irq_level; |
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150 | new_ipl = ipl_table[vector]; |
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151 | if (new_ipl > old_ipl) /* Ignore spurious interrupt */ |
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152 | irq_level = new_ipl; |
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153 | update_mask(); |
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154 | |||
155 | /* Allow another interrupt that has higher priority */
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156 | splon(); |
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157 | |||
158 | /* Dispatch interrupt */
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159 | irq_handler(vector); |
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160 | |||
161 | sploff(); |
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162 | |||
163 | /* Restore interrupt level */
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164 | irq_level = old_ipl; |
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165 | update_mask(); |
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166 | out:
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167 | return;
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168 | } |
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169 | |||
170 | /*
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171 | * Initialize interrupt controllers.
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172 | * All interrupts will be masked off.
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173 | */
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174 | void
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175 | interrupt_init(void)
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176 | { |
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177 | int i;
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178 | |||
179 | irq_level = IPL_NONE; |
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180 | |||
181 | for (i = 0; i < NIRQS; i++) |
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182 | ipl_table[i] = IPL_NONE; |
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183 | |||
184 | for (i = 0; i < NIPLS; i++) |
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185 | mask_table[i] = 0;
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186 | |||
187 | ICU_IRQENCLR = 0xffff; /* Mask all interrupts */ |
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188 | } |