scoutos / prex-0.9.0 / bsp / hal / arm / include / mmu.h @ 03e9c04a
History | View | Annotate | Download (2.62 KB)
1 |
/*-
|
---|---|
2 |
* Copyright (c) 2005-2008, Kohsuke Ohtani
|
3 |
* All rights reserved.
|
4 |
*
|
5 |
* Redistribution and use in source and binary forms, with or without
|
6 |
* modification, are permitted provided that the following conditions
|
7 |
* are met:
|
8 |
* 1. Redistributions of source code must retain the above copyright
|
9 |
* notice, this list of conditions and the following disclaimer.
|
10 |
* 2. Redistributions in binary form must reproduce the above copyright
|
11 |
* notice, this list of conditions and the following disclaimer in the
|
12 |
* documentation and/or other materials provided with the distribution.
|
13 |
* 3. Neither the name of the author nor the names of any co-contributors
|
14 |
* may be used to endorse or promote products derived from this software
|
15 |
* without specific prior written permission.
|
16 |
*
|
17 |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
18 |
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
19 |
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
20 |
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
21 |
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
22 |
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
23 |
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
24 |
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
25 |
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
26 |
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
27 |
* SUCH DAMAGE.
|
28 |
*/
|
29 |
|
30 |
#ifndef _ARM_MMU_H
|
31 |
#define _ARM_MMU_H
|
32 |
|
33 |
#include <sys/types.h> |
34 |
|
35 |
typedef uint32_t *pgd_t; /* page directory */ |
36 |
typedef uint32_t *pte_t; /* page table entry */ |
37 |
|
38 |
#define L1TBL_SIZE 0x4000 |
39 |
#define L2TBL_SIZE 0x1000 |
40 |
|
41 |
/*
|
42 |
* Page directory entry (L1)
|
43 |
*/
|
44 |
#define PDE_PRESENT 0x00000003 |
45 |
#define PDE_ADDRESS 0xfffff000 |
46 |
|
47 |
/*
|
48 |
* Page table entry (L2)
|
49 |
*/
|
50 |
#define PTE_PRESENT 0x00000002 |
51 |
#define PTE_WBUF 0x00000004 |
52 |
#define PTE_CACHE 0x00000008 |
53 |
#define PTE_SYSTEM 0x00000010 |
54 |
#define PTE_USER_RO 0x00000020 |
55 |
#define PTE_USER_RW 0x00000030 |
56 |
#define PTE_ATTR_MASK 0x00000030 |
57 |
#define PTE_ADDRESS 0xfffffc00 |
58 |
|
59 |
/*
|
60 |
* Virtual and physical address translation
|
61 |
*/
|
62 |
#define PAGE_DIR(virt) (int)((((vaddr_t)(virt)) >> 20) & 0xfff) |
63 |
#define PAGE_TABLE(virt) (int)((((vaddr_t)(virt)) >> 12) & 0xff) |
64 |
|
65 |
#define pte_present(pgd, virt) (pgd[PAGE_DIR(virt)] & PDE_PRESENT)
|
66 |
|
67 |
#define page_present(pte, virt) (pte[PAGE_TABLE(virt)] & PTE_PRESENT)
|
68 |
|
69 |
#define vtopte(pgd, virt) \
|
70 |
(pte_t)ptokv((pgd)[PAGE_DIR(virt)] & PDE_ADDRESS) |
71 |
|
72 |
#define ptetopg(pte, virt) \
|
73 |
((pte)[PAGE_TABLE(virt)] & PTE_ADDRESS) |
74 |
|
75 |
|
76 |
#endif /* !_ARM_MMU_H */ |