scoutos / prex-0.9.0 / bsp / hal / arm / arch / cpufunc.S @ 03e9c04a
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/*- |
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* Copyright (c) 2008, Kohsuke Ohtani |
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* All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. Neither the name of the author nor the names of any co-contributors |
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* may be used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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*/ |
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|
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/* |
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* cpufunc.S - ARM specific CPU functions |
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*/ |
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|
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#include <conf/config.h> |
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#include <machine/asm.h> |
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#include <cpu.h> |
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|
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.section ".text","ax" |
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.code 32 |
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|
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ENTRY(cpu_idle) |
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#if 0 |
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mcr p15, 0, r0, c7, c0, 4 /* Wait for interrupt */ |
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#endif |
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mov pc, lr |
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|
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/* |
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* Fault information |
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*/ |
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ENTRY(get_faultstatus) |
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mrc p15, 0, r0, c5, c0, 0 |
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mov pc, lr |
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|
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ENTRY(get_faultaddress) |
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mrc p15, 0, r0, c6, c0, 0 |
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mov pc, lr |
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|
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|
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#ifdef CONFIG_MMU |
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/* |
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* Get TTB - Translation Table Base register |
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*/ |
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ENTRY(get_ttb) |
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mrc p15, 0, r0, c2, c0, 0 |
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mov pc, lr |
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|
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/* |
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* Set TTB |
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*/ |
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ENTRY(set_ttb) |
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mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ |
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mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ |
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nop |
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nop |
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nop |
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mov pc, lr |
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|
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/* |
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* Switch TTB for context switch |
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*/ |
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ENTRY(switch_ttb) |
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mcr p15, 0, r0, c7, c5, 0 /* flush I cache */ |
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mcr p15, 0, r0, c7, c6, 0 /* flush D cache */ |
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ |
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mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */ |
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mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */ |
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nop |
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nop |
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nop |
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mov pc, lr |
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|
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/* |
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* Flush TLB |
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*/ |
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ENTRY(flush_tlb) |
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mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ |
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mov pc, lr |
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|
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#endif /* !CONFIG_MMU */ |
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|
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/* |
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* Flush all cache |
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*/ |
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ENTRY(flush_cache) |
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mcr p15, 0, r0, c7, c5, 0 /* flush I cache */ |
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mcr p15, 0, r0, c7, c6, 0 /* flush D cache */ |
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ |
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mov pc, lr |
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|
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.end |