scoutos / prex-0.9.0 / bsp / hal / x86 / arch / locore.S @ 03e9c04a
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1 | 03e9c04a | Brad Neuman | /*- |
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2 | * Copyright (c) 2005-2008, Kohsuke Ohtani |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * 1. Redistributions of source code must retain the above copyright |
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9 | * notice, this list of conditions and the following disclaimer. |
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10 | * 2. Redistributions in binary form must reproduce the above copyright |
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11 | * notice, this list of conditions and the following disclaimer in the |
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12 | * documentation and/or other materials provided with the distribution. |
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13 | * 3. Neither the name of the author nor the names of any co-contributors |
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14 | * may be used to endorse or promote products derived from this software |
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15 | * without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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27 | * SUCH DAMAGE. |
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28 | */ |
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29 | |||
30 | /* |
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31 | * locore.S - low level platform support |
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32 | */ |
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33 | |||
34 | #include <conf/config.h> |
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35 | #include <machine/asm.h> |
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36 | #include <machine/syspage.h> |
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37 | #include <machine/memory.h> |
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38 | #include <sys/errno.h> |
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39 | #include <cpu.h> |
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40 | |||
41 | /* |
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42 | * Macro to save/restore registers |
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43 | * |
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44 | * This macro builds the trap frame by pushing registers. |
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45 | * If you change the push order of these macro, you must change the |
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46 | * trap frame structure in arch.h. In addition, the system call stub |
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47 | * will depend on this register format. |
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48 | */ |
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49 | #define SAVE_ALL \ |
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50 | cld; \ |
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51 | pushl %es; \ |
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52 | pushl %ds; \ |
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53 | pushl %ebp; \ |
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54 | pushl %edi; \ |
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55 | pushl %eax; \ |
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56 | pushl %esi; \ |
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57 | pushl %edx; \ |
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58 | pushl %ecx; \ |
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59 | pushl %ebx; |
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60 | |||
61 | #define RESTORE_ALL \ |
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62 | popl %ebx; \ |
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63 | popl %ecx; \ |
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64 | popl %edx; \ |
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65 | popl %esi; \ |
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66 | popl %eax; \ |
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67 | popl %edi; \ |
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68 | popl %ebp; \ |
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69 | popl %ds; \ |
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70 | popl %es; |
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71 | |||
72 | #define SETUP_SEG \ |
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73 | movl $(KERNEL_DS), %edx; \ |
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74 | movl %edx, %ds; \ |
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75 | movl %edx, %es; |
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76 | |||
77 | .section ".text" |
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78 | |||
79 | /* |
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80 | * Kernel start point |
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81 | * |
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82 | * The kernel assumes that the following state is already set by |
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83 | * the kernel loader. |
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84 | * - CPU is in protected mode |
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85 | * - Segment registers are set as 32-bit flat segment |
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86 | * - A20 line is enabled for 32-bit addressing |
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87 | * - Paging is turned off |
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88 | * - The boot information is loaded to address 1000h-1fffh |
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89 | */ |
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90 | /* |
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91 | * Note: The linker will generate an address for kernel_start as 0x80010000. |
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92 | * But, the loader will load the kernel to 0x10000 (physical address). |
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93 | * So, the linear address pointer can not be used until paging is enabled. |
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94 | */ |
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95 | ENTRY(kernel_start) |
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96 | cli /* Disable interrupt */ |
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97 | cld |
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98 | |||
99 | /* |
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100 | * Setup CPU registers. |
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101 | */ |
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102 | movl %cr0, %eax /* Enable kernel write protection */ |
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103 | orl $(CR0_WP), %eax |
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104 | movl %eax, %cr0 |
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105 | |||
106 | pushfl /* Clear nested task, iopl = 0 */ |
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107 | popl %eax |
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108 | andl $~(EFL_IOPL|EFL_NT), %eax |
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109 | pushl %eax |
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110 | popfl |
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111 | |||
112 | #ifdef CONFIG_MMU |
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113 | /* |
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114 | * Initialize page table. |
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115 | * The physical address 0-4M is mapped on virtual address 2G. |
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116 | */ |
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117 | movl $(BOOT_PGD_PHYS), %edi /* Setup kernel page directory */ |
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118 | xorl %eax, %eax /* Invalidate all address */ |
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119 | movl $0x1000, %ecx |
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120 | rep |
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121 | stosb |
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122 | movl $(BOOT_PGD_PHYS+0x800), %edi |
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123 | movl $(BOOT_PTE0_PHYS+0x07), (%edi) |
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124 | movl $1024, %ecx /* Fill boot page table entry */ |
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125 | movl $(BOOT_PTE0_PHYS), %edi |
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126 | movl $0007, %eax |
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127 | fill_pte0: |
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128 | stosl |
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129 | add $0x1000, %eax /* Process next page */ |
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130 | loop fill_pte0 |
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131 | |||
132 | /* |
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133 | * Enable paging. |
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134 | * The physical address 0-4M is temporarily mapped to virtial |
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135 | * address 0-4M. This is needed to enable paging. |
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136 | */ |
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137 | movl $(BOOT_PGD_PHYS), %edi /* Map address 0-4M */ |
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138 | movl $(BOOT_PTE0_PHYS+0x07), (%edi) |
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139 | movl $(BOOT_PGD_PHYS), %eax /* Set page directory pointer */ |
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140 | movl %eax, %cr3 |
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141 | movl %cr0, %eax /* Enable paging bit */ |
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142 | orl $(CR0_PG), %eax |
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143 | movl %eax, %cr0 |
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144 | jmp pipeline_flush /* Flush processor pipeline */ |
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145 | pipeline_flush: |
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146 | movl $cs_reset, %eax |
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147 | jmp *%eax |
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148 | cs_reset: |
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149 | movl $(BOOT_PGD), %edi /* Unmap 0-4M */ |
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150 | movl $0, (%edi) |
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151 | movl %cr3, %eax |
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152 | movl %eax, %cr3 |
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153 | |||
154 | #endif /* CONFIG_MMU */ |
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155 | |||
156 | /* |
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157 | * Clear kernel BSS |
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158 | */ |
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159 | xorl %eax, %eax |
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160 | movl $__bss, %edi |
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161 | movl $__end, %ecx |
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162 | subl %edi, %ecx |
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163 | rep |
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164 | stosb |
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165 | |||
166 | /* |
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167 | * Setup boot stack |
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168 | */ |
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169 | movl $(BOOTSTK), %edi |
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170 | movl $(BOOTSTKSZ), %ecx |
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171 | rep |
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172 | stosb |
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173 | movl $(BOOTSTKTOP), %esp |
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174 | movl %esp, %ebp |
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175 | |||
176 | movl $15, curspl |
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177 | |||
178 | /* |
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179 | * Call kernel main routine |
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180 | */ |
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181 | call main |
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182 | /* NOTREACHED */ |
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183 | cli |
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184 | hlt |
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185 | |||
186 | /* |
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187 | * Common entry for all interrupts |
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188 | * Setup interrupt stack for outermost interrupt. |
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189 | * The code should be written to prevent the stack overflow |
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190 | * by continuous interrupt as much as it can. |
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191 | */ |
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192 | ENTRY(interrupt_common) |
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193 | SAVE_ALL |
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194 | SETUP_SEG |
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195 | incl irq_nesting /* Increment nesting level */ |
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196 | cmpl $1, irq_nesting /* Outermost interrupt ? */ |
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197 | jne nested_irq |
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198 | mov %esp, %ebp /* Save current stack */ |
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199 | movl $(INTSTKTOP), %esp /* Switch stack */ |
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200 | call sched_lock /* Lock scheduler */ |
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201 | pushl %ebp /* Push trap frame */ |
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202 | call interrupt_handler /* Process interrupt */ |
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203 | movl %ebp, %esp /* Restore original stack */ |
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204 | decl irq_nesting |
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205 | call sched_unlock /* Try to preempt */ |
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206 | testl $3, 0x30(%esp) /* Return to kernel mode ? */ |
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207 | jz interrupt_ret /* Skip exception if kernel mode */ |
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208 | sti |
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209 | call exception_deliver /* Check exception */ |
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210 | interrupt_ret: |
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211 | cli |
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212 | RESTORE_ALL |
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213 | addl $8, %esp |
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214 | iret |
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215 | nested_irq: |
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216 | push %esp /* Push trap frame */ |
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217 | call interrupt_handler /* Process interrupt */ |
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218 | addl $4, %esp |
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219 | decl irq_nesting |
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220 | jmp interrupt_ret |
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221 | |||
222 | /* |
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223 | * Macro to build interrupt entry |
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224 | */ |
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225 | #define INTR_ENTRY(irq) \ |
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226 | ENTRY(intr_##irq) \ |
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227 | pushl $0; \ |
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228 | pushl $(irq); \ |
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229 | jmp interrupt_common |
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230 | |||
231 | INTR_ENTRY(0) |
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232 | INTR_ENTRY(1) |
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233 | INTR_ENTRY(2) |
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234 | INTR_ENTRY(3) |
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235 | INTR_ENTRY(4) |
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236 | INTR_ENTRY(5) |
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237 | INTR_ENTRY(6) |
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238 | INTR_ENTRY(7) |
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239 | INTR_ENTRY(8) |
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240 | INTR_ENTRY(9) |
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241 | INTR_ENTRY(10) |
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242 | INTR_ENTRY(11) |
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243 | INTR_ENTRY(12) |
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244 | INTR_ENTRY(13) |
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245 | INTR_ENTRY(14) |
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246 | INTR_ENTRY(15) |
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247 | |||
248 | /* |
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249 | * Common entry for all traps |
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250 | * New thread will start from trap_ret. |
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251 | */ |
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252 | ENTRY(trap_common) |
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253 | SAVE_ALL |
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254 | SETUP_SEG |
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255 | pushl %esp |
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256 | call trap_handler |
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257 | addl $4, %esp |
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258 | trap_ret: |
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259 | RESTORE_ALL |
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260 | addl $8, %esp |
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261 | iret |
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262 | |||
263 | /* |
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264 | * Default trap entry |
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265 | */ |
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266 | ENTRY(trap_default) |
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267 | pushl $0 |
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268 | pushl $(INVALID_INT) |
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269 | jmp trap_common |
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270 | |||
271 | /* |
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272 | * Macro to build trap entry |
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273 | * Some trap will push the error code into stack. |
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274 | */ |
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275 | #define TRAP_ENTRY(id) \ |
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276 | ENTRY(trap_##id) \ |
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277 | pushl $0; \ |
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278 | pushl $(id); \ |
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279 | jmp trap_common; |
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280 | |||
281 | #define TRAP_ERR_ENTRY(id) \ |
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282 | ENTRY(trap_##id) \ |
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283 | pushl $(id); \ |
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284 | jmp trap_common; |
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285 | |||
286 | TRAP_ENTRY ( 0) /* Divide error */ |
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287 | TRAP_ENTRY ( 1) /* Debug trap */ |
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288 | TRAP_ENTRY ( 2) /* NMI */ |
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289 | TRAP_ENTRY ( 3) /* Breakpoint */ |
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290 | TRAP_ENTRY ( 4) /* Overflow */ |
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291 | TRAP_ENTRY ( 5) /* Bounds check */ |
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292 | TRAP_ENTRY ( 6) /* Invalid opecode */ |
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293 | TRAP_ENTRY ( 7) /* Device not available */ |
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294 | TRAP_ERR_ENTRY( 8) /* Double fault */ |
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295 | TRAP_ERR_ENTRY( 9) /* Coprocessor overrun */ |
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296 | TRAP_ERR_ENTRY(10) /* Invalid TSS */ |
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297 | TRAP_ERR_ENTRY(11) /* Segment not present */ |
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298 | TRAP_ERR_ENTRY(12) /* Stack bounds */ |
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299 | TRAP_ERR_ENTRY(13) /* General Protection */ |
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300 | TRAP_ERR_ENTRY(14) /* Page fault */ |
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301 | TRAP_ENTRY (15) /* (reserved) */ |
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302 | TRAP_ENTRY (16) /* Coprocessor error */ |
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303 | TRAP_ERR_ENTRY(17) /* Alignment check */ |
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304 | TRAP_ERR_ENTRY(18) /* Cache flush denied */ |
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305 | |||
306 | |||
307 | /* |
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308 | * System call entry |
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309 | */ |
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310 | .global syscall_ret |
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311 | ENTRY(syscall_entry) |
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312 | pushl $0 /* Dummy for error code */ |
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313 | pushl $(SYSCALL_INT) /* Trap number */ |
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314 | SAVE_ALL |
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315 | SETUP_SEG |
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316 | call syscall_handler |
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317 | cmpl $0, 0x10(%esp) /* Skip setting eax if exception_return */ |
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318 | je 1f |
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319 | movl %eax, 0x10(%esp) /* Set return value to eax */ |
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320 | 1: |
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321 | call exception_deliver /* Check exception */ |
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322 | syscall_ret: |
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323 | RESTORE_ALL |
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324 | addl $8, %esp /* Discard err/trap no */ |
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325 | iret |
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326 | |||
327 | /* |
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328 | * Switch register context. |
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329 | * Interrupts must be disabled by caller. |
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330 | * |
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331 | * syntax - void cpu_switch(kern_regs *prev, kern_regs *next) |
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332 | * |
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333 | * Note: GCC assumes ebx,ebp,edi,esi registers are not changed in each routine. |
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334 | */ |
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335 | ENTRY(cpu_switch) |
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336 | movl 4(%esp), %ecx /* Point ecx to previous registers */ |
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337 | movl (%esp), %eax /* Get return address */ |
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338 | movl %eax, 0(%ecx) /* Save it as eip */ |
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339 | movl %ebx, 4(%ecx) /* Save ebx */ |
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340 | movl %edi, 8(%ecx) /* Save edi */ |
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341 | movl %esi, 12(%ecx) /* Save esi */ |
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342 | movl %ebp, 16(%ecx) /* Save ebp */ |
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343 | movl %esp, 20(%ecx) /* Save esp */ |
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344 | movl 8(%esp), %ecx /* Point ecx to next registers */ |
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345 | movl 4(%ecx), %ebx /* Restore ebx */ |
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346 | movl 8(%ecx), %edi /* Restore edi */ |
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347 | movl 12(%ecx), %esi /* Restore esp */ |
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348 | movl 16(%ecx), %ebp /* Restore ebp */ |
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349 | movl 20(%ecx), %esp /* Restore esp */ |
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350 | movl 0(%ecx), %eax /* Get eip */ |
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351 | movl %eax, (%esp) /* Restore it as return address */ |
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352 | ret |
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353 | |||
354 | /* |
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355 | * Copy data from user to kernel space. |
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356 | * Returns 0 on success, or EFAULT on page fault. |
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357 | * |
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358 | * syntax - int copyin(const void *uaddr, void *kaddr, size_t len) |
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359 | */ |
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360 | .global known_fault1 |
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361 | ENTRY(copyin) |
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362 | pushl %esi |
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363 | pushl %edi |
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364 | pushl $(EFAULT) /* Set EFAULT as default return */ |
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365 | |||
366 | movl 16(%esp), %esi |
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367 | movl 20(%esp), %edi |
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368 | movl 24(%esp), %ecx |
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369 | |||
370 | movl %esi, %edx /* Check if valid user address */ |
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371 | addl %ecx, %edx |
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372 | jc copy_fault |
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373 | cmpl $(USERLIMIT), %edx /* User area? */ |
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374 | jae copy_fault |
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375 | cld |
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376 | known_fault1: /* May be fault here */ |
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377 | rep |
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378 | movsb |
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379 | |||
380 | popl %eax |
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381 | xorl %eax, %eax /* Set no error */ |
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382 | popl %edi |
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383 | popl %esi |
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384 | ret |
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385 | |||
386 | /* |
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387 | * Copy data to user from kernel space. |
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388 | * Returns 0 on success, or EFAULT on page fault. |
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389 | * |
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390 | * syntax - int copyout(const void *kaddr, void *uaddr, size_t len) |
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391 | */ |
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392 | .global known_fault2 |
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393 | ENTRY(copyout) |
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394 | pushl %esi |
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395 | pushl %edi |
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396 | pushl $(EFAULT) /* Set EFAULT as default return */ |
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397 | |||
398 | movl 16(%esp), %esi |
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399 | movl 20(%esp), %edi |
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400 | movl 24(%esp), %ecx |
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401 | |||
402 | movl %edi, %edx |
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403 | addl %ecx, %edx |
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404 | jc copy_fault |
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405 | cmpl $(USERLIMIT), %edx /* User area? */ |
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406 | jae copy_fault |
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407 | cld |
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408 | known_fault2: /* May be fault here */ |
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409 | rep |
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410 | movsb |
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411 | |||
412 | popl %eax |
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413 | xorl %eax, %eax /* Set no error */ |
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414 | popl %edi |
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415 | popl %esi |
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416 | ret |
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417 | |||
418 | /** |
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419 | * copyinstr - Copy string from user space. |
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420 | * Returns 0 on success, or EFAULT on page fault, or ENAMETOOLONG. |
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421 | * |
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422 | * syntax - int copyinstr(const char *uaddr, void *kaddr, size_t len); |
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423 | * |
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424 | * Note: The returned length value does NOT include the NULL terminator. |
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425 | */ |
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426 | .global known_fault3 |
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427 | ENTRY(copyinstr) |
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428 | pushl %esi |
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429 | pushl %edi |
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430 | pushl $(EFAULT) /* Set EFAULT as default return */ |
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431 | |||
432 | movl 16(%esp), %esi |
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433 | movl 20(%esp), %edi |
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434 | movl 24(%esp), %ecx |
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435 | |||
436 | movl %esi, %edx /* Check if valid user address */ |
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437 | addl %ecx, %edx |
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438 | jc copy_fault |
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439 | cmpl $(USERLIMIT), %edx /* User area? */ |
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440 | jae copy_fault |
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441 | cld |
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442 | jmp 2f |
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443 | 1: |
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444 | decl %ecx |
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445 | jz copyin_toolong |
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446 | 2: |
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447 | known_fault3: /* May be fault here */ |
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448 | lodsb |
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449 | stosb |
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450 | testb %al, %al |
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451 | jnz 1b |
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452 | |||
453 | popl %eax |
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454 | xorl %eax, %eax /* Set no error */ |
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455 | popl %edi |
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456 | popl %esi |
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457 | ret |
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458 | |||
459 | copyin_toolong: |
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460 | popl %eax |
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461 | movl $(ENAMETOOLONG), %eax |
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462 | popl %edi |
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463 | popl %esi |
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464 | ret |
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465 | |||
466 | /* |
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467 | * Fault entry for user access |
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468 | */ |
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469 | ENTRY(copy_fault) |
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470 | popl %eax /* Get return value from stack */ |
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471 | popl %edi |
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472 | popl %esi |
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473 | ret |
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474 | |||
475 | /* |
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476 | * Reset cpu |
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477 | * Use triple fault |
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478 | */ |
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479 | ENTRY(cpu_reset) |
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480 | cli |
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481 | movl $null_idt, %eax /* Reset by triple fault */ |
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482 | lidt (%eax) |
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483 | int $3 |
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484 | hlt |
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485 | |||
486 | .align 4 |
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487 | null_idt: |
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488 | .word 0 |
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489 | .long 0 |
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490 | |||
491 | /* |
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492 | * Initialize cache. |
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493 | */ |
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494 | ENTRY(cache_init) |
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495 | movl %cr0, %eax /* Clear cache disable bit */ |
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496 | andl $~(CR0_CD), %eax |
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497 | movl %eax, %cr0 |
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498 | ret |
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499 | |||
500 | /* |
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501 | * void splx(int s); |
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502 | */ |
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503 | ENTRY(splx) |
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504 | cli |
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505 | movl 4(%esp), %eax |
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506 | movl %eax, curspl |
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507 | cmpl $0, %eax |
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508 | ja 1f |
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509 | sti |
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510 | 1: |
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511 | ret |
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512 | |||
513 | /* |
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514 | * int splhigh(void); |
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515 | */ |
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516 | ENTRY(splhigh) |
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517 | cli |
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518 | movl curspl, %eax |
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519 | movl $15, curspl |
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520 | ret |
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521 | |||
522 | /* |
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523 | * int spl0(void); |
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524 | */ |
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525 | ENTRY(spl0) |
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526 | movl curspl, %eax |
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527 | movl $0, curspl |
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528 | sti |
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529 | ret |
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530 | |||
531 | /* |
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532 | * Disable interrupts |
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533 | */ |
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534 | ENTRY(sploff) |
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535 | cli |
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536 | ret |
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537 | |||
538 | /* |
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539 | * Enable interrupts |
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540 | */ |
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541 | ENTRY(splon) |
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542 | sti |
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543 | ret |
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544 | |||
545 | /* |
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546 | * Interrupt nest counter. |
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547 | * |
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548 | * This counter is incremented in the entry of interrupt handler |
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549 | * to switch the interrupt stack. Since all interrupt handlers |
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550 | * share same one interrupt stack, each handler must pay attention |
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551 | * to the stack overflow. |
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552 | */ |
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553 | .section ".bss" |
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554 | irq_nesting: |
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555 | .long 0 |
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556 | |||
557 | /* |
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558 | * Current spl |
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559 | */ |
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560 | curspl: |
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561 | .long 0 |