scoutos / prex-0.9.0 / bsp / hal / arm / arch / cpufunc.S @ 03e9c04a
History | View | Annotate | Download (2.86 KB)
1 | 03e9c04a | Brad Neuman | /*- |
---|---|---|---|
2 | * Copyright (c) 2008, Kohsuke Ohtani |
||
3 | * All rights reserved. |
||
4 | * |
||
5 | * Redistribution and use in source and binary forms, with or without |
||
6 | * modification, are permitted provided that the following conditions |
||
7 | * are met: |
||
8 | * 1. Redistributions of source code must retain the above copyright |
||
9 | * notice, this list of conditions and the following disclaimer. |
||
10 | * 2. Redistributions in binary form must reproduce the above copyright |
||
11 | * notice, this list of conditions and the following disclaimer in the |
||
12 | * documentation and/or other materials provided with the distribution. |
||
13 | * 3. Neither the name of the author nor the names of any co-contributors |
||
14 | * may be used to endorse or promote products derived from this software |
||
15 | * without specific prior written permission. |
||
16 | * |
||
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
||
18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||
19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||
20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
||
21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||
22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
||
23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
||
24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
||
25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
||
26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
||
27 | * SUCH DAMAGE. |
||
28 | */ |
||
29 | |||
30 | /* |
||
31 | * cpufunc.S - ARM specific CPU functions |
||
32 | */ |
||
33 | |||
34 | #include <conf/config.h> |
||
35 | #include <machine/asm.h> |
||
36 | #include <cpu.h> |
||
37 | |||
38 | .section ".text","ax" |
||
39 | .code 32 |
||
40 | |||
41 | ENTRY(cpu_idle) |
||
42 | #if 0 |
||
43 | mcr p15, 0, r0, c7, c0, 4 /* Wait for interrupt */ |
||
44 | #endif |
||
45 | mov pc, lr |
||
46 | |||
47 | /* |
||
48 | * Fault information |
||
49 | */ |
||
50 | ENTRY(get_faultstatus) |
||
51 | mrc p15, 0, r0, c5, c0, 0 |
||
52 | mov pc, lr |
||
53 | |||
54 | ENTRY(get_faultaddress) |
||
55 | mrc p15, 0, r0, c6, c0, 0 |
||
56 | mov pc, lr |
||
57 | |||
58 | |||
59 | #ifdef CONFIG_MMU |
||
60 | /* |
||
61 | * Get TTB - Translation Table Base register |
||
62 | */ |
||
63 | ENTRY(get_ttb) |
||
64 | mrc p15, 0, r0, c2, c0, 0 |
||
65 | mov pc, lr |
||
66 | |||
67 | /* |
||
68 | * Set TTB |
||
69 | */ |
||
70 | ENTRY(set_ttb) |
||
71 | mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ |
||
72 | mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ |
||
73 | nop |
||
74 | nop |
||
75 | nop |
||
76 | mov pc, lr |
||
77 | |||
78 | /* |
||
79 | * Switch TTB for context switch |
||
80 | */ |
||
81 | ENTRY(switch_ttb) |
||
82 | mcr p15, 0, r0, c7, c5, 0 /* flush I cache */ |
||
83 | mcr p15, 0, r0, c7, c6, 0 /* flush D cache */ |
||
84 | mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ |
||
85 | mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */ |
||
86 | mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */ |
||
87 | nop |
||
88 | nop |
||
89 | nop |
||
90 | mov pc, lr |
||
91 | |||
92 | /* |
||
93 | * Flush TLB |
||
94 | */ |
||
95 | ENTRY(flush_tlb) |
||
96 | mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ |
||
97 | mov pc, lr |
||
98 | |||
99 | #endif /* !CONFIG_MMU */ |
||
100 | |||
101 | /* |
||
102 | * Flush all cache |
||
103 | */ |
||
104 | ENTRY(flush_cache) |
||
105 | mcr p15, 0, r0, c7, c5, 0 /* flush I cache */ |
||
106 | mcr p15, 0, r0, c7, c6, 0 /* flush D cache */ |
||
107 | mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ |
||
108 | mov pc, lr |
||
109 | |||
110 | .end |