Revision 660
stop.c actually does what the folder title implies
It only looks at the homing data and the contact stuff and sends it to the robot
branches/autonomous_recharging/code/projects/autonomous_recharging/archs/homing stop/USI_TWI_Master.c | ||
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/***************************************************************************** |
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* |
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* Atmel Corporation |
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* |
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* File : USI_TWI_Master.c |
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* Compiler : IAR EWAAVR 2.28a/3.10a |
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* Revision : $Revision: 1.11 $ |
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* Date : $Date: Tuesday, September 13, 2005 09:09:36 UTC $ |
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* Updated by : $Author: jtyssoe $ |
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* |
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* Support mail : avr@atmel.com |
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* |
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* Supported devices : All device with USI module can be used. |
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* The example is written for the ATmega169, ATtiny26 and ATtiny2313 |
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* |
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* AppNote : AVR310 - Using the USI module as a TWI Master |
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* |
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* Description : This is an implementation of an TWI master using |
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* the USI module as basis. The implementation assumes the AVR to |
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* be the only TWI master in the system and can therefore not be |
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* used in a multi-master system. |
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* Usage : Initialize the USI module by calling the USI_TWI_Master_Initialise() |
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* function. Hence messages/data are transceived on the bus using |
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* the USI_TWI_Transceive() function. The transceive function |
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* returns a status byte, which can be used to evaluate the |
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* success of the transmission. |
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* |
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****************************************************************************/ |
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#ifndef _USI_TWI_MASTER_H |
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#define _USI_TWI_MASTER_H |
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#include <util/delay.h> |
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#include <avr/io.h> |
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#include <avr/interrupt.h> |
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#include "USI_TWI_Master.h" |
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unsigned char USI_TWI_Master_Transfer( unsigned char ); |
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unsigned char USI_TWI_Master_Stop( void ); |
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|
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union USI_TWI_state |
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{ |
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unsigned char errorState; // Can reuse the TWI_state for error states due to that it will not be need if there exists an error. |
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struct |
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{ |
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unsigned char addressMode : 1; |
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unsigned char masterWriteDataMode : 1; |
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unsigned char unused : 6; |
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}; |
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} USI_TWI_state; |
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|
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/*--------------------------------------------------------------- |
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USI TWI single master initialization function |
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---------------------------------------------------------------*/ |
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void USI_TWI_Master_Initialise( void ) |
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{ |
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PORT_USI |= (1<<PIN_USI_SDA); // Enable pullup on SDA, to set high as released state. |
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PORT_USI |= (1<<PIN_USI_SCL); // Enable pullup on SCL, to set high as released state. |
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|
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DDR_USI |= (1<<PIN_USI_SCL); // Enable SCL as output. |
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DDR_USI |= (1<<PIN_USI_SDA); // Enable SDA as output. |
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|
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USIDR = 0xFF; // Preload dataregister with "released level" data. |
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USICR = (0<<USISIE)|(0<<USIOIE)| // Disable Interrupts. |
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(1<<USIWM1)|(0<<USIWM0)| // Set USI in Two-wire mode. |
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(1<<USICS1)|(0<<USICS0)|(1<<USICLK)| // Software stobe as counter clock source |
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(0<<USITC); |
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USISR = (1<<USISIF)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| // Clear flags, |
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(0x0<<USICNT0); // and reset counter. |
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} |
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|
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/*--------------------------------------------------------------- |
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Use this function to get hold of the error message from the last transmission |
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---------------------------------------------------------------*/ |
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unsigned char USI_TWI_Get_State_Info( void ) |
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{ |
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return ( USI_TWI_state.errorState ); // Return error state. |
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} |
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|
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/*--------------------------------------------------------------- |
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USI Transmit and receive function. LSB of first byte in data |
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indicates if a read or write cycles is performed. If set a read |
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operation is performed. |
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|
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Function generates (Repeated) Start Condition, sends address and |
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R/W, Reads/Writes Data, and verifies/sends ACK. |
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Success or error code is returned. Error codes are defined in |
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USI_TWI_Master.h |
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---------------------------------------------------------------*/ |
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unsigned char USI_TWI_Start_Transceiver_With_Data( unsigned char *msg, unsigned char msgSize) |
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{ |
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unsigned char tempUSISR_8bit = (1<<USISIF)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| // Prepare register value to: Clear flags, and |
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(0x0<<USICNT0); // set USI to shift 8 bits i.e. count 16 clock edges. |
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unsigned char tempUSISR_1bit = (1<<USISIF)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| // Prepare register value to: Clear flags, and |
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(0xE<<USICNT0); // set USI to shift 1 bit i.e. count 2 clock edges. |
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USI_TWI_state.errorState = 0; |
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USI_TWI_state.addressMode = TRUE; |
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if ( !(*msg & (1<<TWI_READ_BIT)) ) // The LSB in the address byte determines if is a masterRead or masterWrite operation. |
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{ |
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USI_TWI_state.masterWriteDataMode = TRUE; |
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} |
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/* Release SCL to ensure that (repeated) Start can be performed */ |
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PORT_USI |= (1<<PIN_USI_SCL); // Release SCL. |
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while( !(PORT_USI & (1<<PIN_USI_SCL)) ); // Verify that SCL becomes high. |
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_delay_loop_1(T2_TWI); |
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//_delay_us(T4_TWI); |
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//__delay_cycles( T2_TWI ); // Delay for T2TWI if TWI_STANDARD_MODE |
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/* Generate Start Condition */ |
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PORT_USI &= ~(1<<PIN_USI_SDA); // Force SDA LOW. |
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_delay_loop_1(T4_TWI); |
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//_delay_us(T4_TWI); |
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//__delay_cycles( T4_TWI ); |
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PORT_USI &= ~(1<<PIN_USI_SCL); // Pull SCL LOW. |
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PORT_USI |= (1<<PIN_USI_SDA); // Release SDA. |
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//Start |
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PORTA |= _BV(PA3); |
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/*Write address and Read/Write data */ |
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do |
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{ |
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/* If masterWrite cycle (or inital address tranmission)*/ |
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if (USI_TWI_state.addressMode || USI_TWI_state.masterWriteDataMode) |
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{ |
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PORTA |= _BV(PA4); |
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/* Write a byte */ |
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PORT_USI &= ~(1<<PIN_USI_SCL); // Pull SCL LOW. |
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USIDR = *(msg++); // Setup data. |
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USI_TWI_Master_Transfer( tempUSISR_8bit ); // Send 8 bits on bus. |
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/* Clock and verify (N)ACK from slave */ |
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DDR_USI &= ~(1<<PIN_USI_SDA); // Enable SDA as input. |
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PORTA |= _BV(PA5); |
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if( USI_TWI_Master_Transfer( tempUSISR_1bit ) & (1<<TWI_NACK_BIT) ) |
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{ |
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//Shit |
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PORTA |= _BV(PA3) | _BV(PA4) | _BV(PA5) | _BV(PA6) | _BV(PA7); |
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if ( USI_TWI_state.addressMode ) |
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USI_TWI_state.errorState = USI_TWI_NO_ACK_ON_ADDRESS; |
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else |
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USI_TWI_state.errorState = USI_TWI_NO_ACK_ON_DATA; |
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return (FALSE); |
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} |
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USI_TWI_state.addressMode = FALSE; // Only perform address transmission once. |
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PORTA &= (~_BV(PA4) | ~_BV(PA5)); |
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} |
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/* Else masterRead cycle*/ |
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else |
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{ |
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/* Read a data byte */ |
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DDR_USI &= ~(1<<PIN_USI_SDA); // Enable SDA as input. |
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*(msg++) = USI_TWI_Master_Transfer( tempUSISR_8bit ); |
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/* Prepare to generate ACK (or NACK in case of End Of Transmission) */ |
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if( msgSize == 1) // If transmission of last byte was performed. |
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{ |
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USIDR = 0xFF; // Load NACK to confirm End Of Transmission. |
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} |
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else |
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{ |
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USIDR = 0x00; // Load ACK. Set data register bit 7 (output for SDA) low. |
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} |
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USI_TWI_Master_Transfer( tempUSISR_1bit ); // Generate ACK/NACK. |
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} |
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}while( --msgSize) ; // Until all data sent/received. |
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PORTA |= _BV(PA6); |
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USI_TWI_Master_Stop(); // Send a STOP condition on the TWI bus. |
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/* Transmission successfully completed*/ |
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return (TRUE); |
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} |
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/*--------------------------------------------------------------- |
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Core function for shifting data in and out from the USI. |
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Data to be sent has to be placed into the USIDR prior to calling |
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this function. Data read, will be return'ed from the function. |
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---------------------------------------------------------------*/ |
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unsigned char USI_TWI_Master_Transfer( unsigned char temp ) |
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{ |
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USISR = temp; // Set USISR according to temp. |
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// Prepare clocking. |
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temp = (0<<USISIE)|(0<<USIOIE)| // Interrupts disabled |
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(1<<USIWM1)|(0<<USIWM0)| // Set USI in Two-wire mode. |
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(1<<USICS1)|(0<<USICS0)|(1<<USICLK)| // Software clock strobe as source. |
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(1<<USITC); // Toggle Clock Port. |
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do |
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{ |
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//__delay_cycles( T2_TWI ); |
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_delay_loop_1(T2_TWI); |
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//_delay_us(T2_TWI); |
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USICR = temp; // Generate positve SCL edge. |
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while( !(PIN_USI & (1<<PIN_USI_SCL)) );// Wait for SCL to go high. |
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_delay_loop_1(T4_TWI); |
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//__delay_cycles( T4_TWI ); |
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// _delay_us(T4_TWI); |
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USICR = temp; // Generate negative SCL edge. |
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}while( !(USISR & (1<<USIOIF)) ); // Check for transfer complete. |
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_delay_loop_1(T2_TWI); |
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//_delay_us(T2_TWI); |
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//__delay_cycles( T2_TWI ); |
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temp = USIDR; // Read out data. |
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USIDR = 0xFF; // Release SDA. |
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DDR_USI |= (1<<PIN_USI_SDA); // Enable SDA as output. |
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return temp; // Return the data from the USIDR |
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} |
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/*--------------------------------------------------------------- |
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Function for generating a TWI Stop Condition. Used to release |
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the TWI bus. |
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---------------------------------------------------------------*/ |
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unsigned char USI_TWI_Master_Stop( void ) |
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{ |
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PORT_USI &= ~(1<<PIN_USI_SDA); // Pull SDA low. |
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PORT_USI |= (1<<PIN_USI_SCL); // Release SCL. |
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while( !(PIN_USI & (1<<PIN_USI_SCL)) ); // Wait for SCL to go high. |
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_delay_loop_1(T4_TWI); |
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//_delay_us(T4_TWI); |
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//__delay_cycles( T4_TWI ); |
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PORT_USI |= (1<<PIN_USI_SDA); // Release SDA. |
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_delay_loop_1(T2_TWI); |
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//_delay_us(T2_TWI); |
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//__delay_cycles( T2_TWI ); |
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#ifdef SIGNAL_VERIFY |
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if( !(USISR & (1<<USIPF)) ) |
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{ |
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USI_TWI_state.errorState = USI_TWI_MISSING_STOP_CON; |
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return (FALSE); |
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} |
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#endif |
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return (TRUE); |
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} |
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#endif |
branches/autonomous_recharging/code/projects/autonomous_recharging/archs/homing stop/USI_TWI_Slave.h | ||
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// This file has been prepared for Doxygen automatic documentation generation. |
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/*! \file ******************************************************************** |
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* |
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* Atmel Corporation |
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* |
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* File : USI_TWI_Slave.h |
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* Compiler : IAR EWAAVR 4.11A |
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* Revision : $Revision: 1.14 $ |
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* Date : $Date: Friday, December 09, 2005 17:25:38 UTC $ |
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* Updated by : $Author: jtyssoe $ |
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* |
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* Support mail : avr@atmel.com |
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* |
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* Supported devices : All device with USI module can be used. |
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* The example is written for the ATmega169, ATtiny26 & ATtiny2313 |
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* |
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* AppNote : AVR312 - Using the USI module as a TWI slave |
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* |
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* Description : Header file for USI_TWI driver |
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* |
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* |
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* |
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****************************************************************************/ |
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|
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//! Prototypes |
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void USI_TWI_Slave_Initialise( unsigned char ); |
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void USI_TWI_Transmit_Byte( unsigned char ); |
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unsigned char USI_TWI_Receive_Byte( void ); |
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unsigned char USI_TWI_Data_In_Receive_Buffer( void ); |
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void Timer_Init(void); |
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#define TRUE 1 |
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#define FALSE 0 |
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typedef unsigned char uint8_t; |
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////////////////////////////////////////////////////////////////// |
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///////////////// Driver Buffer Definitions ////////////////////// |
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////////////////////////////////////////////////////////////////// |
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// 1,2,4,8,16,32,64,128 or 256 bytes are allowed buffer sizes |
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|
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#define TWI_RX_BUFFER_SIZE (16) |
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#define TWI_RX_BUFFER_MASK ( TWI_RX_BUFFER_SIZE - 1 ) |
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#if ( TWI_RX_BUFFER_SIZE & TWI_RX_BUFFER_MASK ) |
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#error TWI RX buffer size is not a power of 2 |
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#endif |
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// 1,2,4,8,16,32,64,128 or 256 bytes are allowed buffer sizes |
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#define TWI_TX_BUFFER_SIZE (16) |
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#define TWI_TX_BUFFER_MASK ( TWI_TX_BUFFER_SIZE - 1 ) |
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#if ( TWI_TX_BUFFER_SIZE & TWI_TX_BUFFER_MASK ) |
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#error TWI TX buffer size is not a power of 2 |
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#endif |
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#define USI_SLAVE_CHECK_ADDRESS (0x00) |
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#define USI_SLAVE_SEND_DATA (0x01) |
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#define USI_SLAVE_REQUEST_REPLY_FROM_SEND_DATA (0x02) |
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#define USI_SLAVE_CHECK_REPLY_FROM_SEND_DATA (0x03) |
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#define USI_SLAVE_REQUEST_DATA (0x04) |
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#define USI_SLAVE_GET_DATA_AND_SEND_ACK (0x05) |
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|
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#define DDR_USI DDRB |
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#define PORT_USI PORTB |
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#define PIN_USI PINB |
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#define PORT_USI_SDA PORTB0 |
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#define PORT_USI_SCL PORTB2 |
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#define PIN_USI_SDA PINB0 |
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#define PIN_USI_SCL PINB2 |
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#define USI_START_COND_INT USISIF |
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#define USI_START_VECTOR USI_START_vect |
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#define USI_OVERFLOW_VECTOR USI_OVF_vect |
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|
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|
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//! Functions implemented as macros |
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#define SET_USI_TO_SEND_ACK() \ |
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{ \ |
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USIDR = 0; /* Prepare ACK */ \ |
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DDR_USI |= (1<<PORT_USI_SDA); /* Set SDA as output */ \ |
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USISR = (0<<USI_START_COND_INT)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| /* Clear all flags, except Start Cond */ \ |
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(0x0E<<USICNT0); /* set USI counter to shift 1 bit. */ \ |
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} |
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|
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#define SET_USI_TO_READ_ACK() \ |
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{ \ |
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DDR_USI &= ~(1<<PORT_USI_SDA); /* Set SDA as intput */ \ |
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USIDR = 0; /* Prepare ACK */ \ |
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USISR = (0<<USI_START_COND_INT)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| /* Clear all flags, except Start Cond */ \ |
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(0x0E<<USICNT0); /* set USI counter to shift 1 bit. */ \ |
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} |
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|
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#define SET_USI_TO_TWI_START_CONDITION_MODE() \ |
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{ \ |
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USICR = (1<<USISIE)|(0<<USIOIE)| /* Enable Start Condition Interrupt. Disable Overflow Interrupt.*/ \ |
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(1<<USIWM1)|(0<<USIWM0)| /* Set USI in Two-wire mode. No USI Counter overflow hold. */ \ |
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(1<<USICS1)|(0<<USICS0)|(0<<USICLK)| /* Shift Register Clock Source = External, positive edge */ \ |
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(0<<USITC); \ |
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USISR = (0<<USI_START_COND_INT)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| /* Clear all flags, except Start Cond */ \ |
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(0x0<<USICNT0); \ |
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} |
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|
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#define SET_USI_TO_SEND_DATA() \ |
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{ \ |
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DDR_USI |= (1<<PORT_USI_SDA); /* Set SDA as output */ \ |
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USISR = (0<<USI_START_COND_INT)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| /* Clear all flags, except Start Cond */ \ |
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(0x0<<USICNT0); /* set USI to shift out 8 bits */ \ |
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} |
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|
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#define SET_USI_TO_READ_DATA() \ |
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{ \ |
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DDR_USI &= ~(1<<PORT_USI_SDA); /* Set SDA as input */ \ |
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USISR = (0<<USI_START_COND_INT)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| /* Clear all flags, except Start Cond */ \ |
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(0x0<<USICNT0); /* set USI to shift out 8 bits */ \ |
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} |
branches/autonomous_recharging/code/projects/autonomous_recharging/archs/homing stop/i2c.h | ||
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/* i2c.h |
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|
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constants and stuff |
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*/ |
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#ifndef _I2C_H_ |
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#define _I2C_H_ |
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|
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#include <avr/io.h> |
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#include <avr/interrupt.h> |
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#include <util/delay.h> |
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|
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#include "USI_TWI_Master.c" |
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#include "USI_TWI_Slave.c" |
|
14 |
#include "i2c.c" |
|
15 |
|
|
16 |
void i2c_init(void); |
|
17 |
void i2c_putpacket(char addr, char *data, char data_size); |
|
18 |
int i2c_getpacket(char *c); |
|
19 |
void i2c_test(void); |
|
20 |
void delay_ms(int ms); |
|
21 |
|
|
22 |
#endif |
branches/autonomous_recharging/code/projects/autonomous_recharging/archs/homing stop/USI_TWI_Master.h | ||
---|---|---|
1 |
|
|
2 |
|
|
3 |
|
|
4 |
/***************************************************************************** |
|
5 |
* |
|
6 |
* Atmel Corporation |
|
7 |
* |
|
8 |
* File : USI_TWI_Master.h |
|
9 |
* Compiler : IAR EWAAVR 2.28a/3.10a |
|
10 |
* Revision : $Revision: 1.11 $ |
|
11 |
* Date : $Date: Tuesday, September 13, 2005 09:09:36 UTC $ |
|
12 |
* Updated by : $Author: jtyssoe $ |
|
13 |
* |
|
14 |
* Support mail : avr@atmel.com |
|
15 |
* |
|
16 |
* Supported devices : All device with USI module can be used. |
|
17 |
* The example is written for the ATmega169, ATtiny26 and ATtiny2313 |
|
18 |
* |
|
19 |
* AppNote : AVR310 - Using the USI module as a TWI Master |
|
20 |
* |
|
21 |
* Description : This is an implementation of an TWI master using |
|
22 |
* the USI module as basis. The implementation assumes the AVR to |
|
23 |
* be the only TWI master in the system and can therefore not be |
|
24 |
* used in a multi-master system. |
|
25 |
* Usage : Initialize the USI module by calling the USI_TWI_Master_Initialise() |
|
26 |
* function. Hence messages/data are transceived on the bus using |
|
27 |
* the USI_TWI_Start_Transceiver_With_Data() function. If the transceiver |
|
28 |
* returns with a fail, then use USI_TWI_Get_Status_Info to evaluate the |
|
29 |
* couse of the failure. |
|
30 |
* |
|
31 |
****************************************************************************/ |
|
32 |
|
|
33 |
//********** Defines **********// |
|
34 |
|
|
35 |
// Defines controlling timing limits |
|
36 |
//#define TWI_FAST_MODE |
|
37 |
|
|
38 |
//#define SYS_CLK 4000.0 // [kHz] |
|
39 |
|
|
40 |
//Note, this is only a variable that determines how long to delay between |
|
41 |
// individual bits of I2C send. This has been tested down to 1MHz and it works. |
|
42 |
// It is possible that even slower speeds can be obtained. |
|
43 |
#define SYS_CLK 1.0 // [mHz] |
|
44 |
|
|
45 |
// TWI FAST mode timing limits. SCL = 100-400kHz |
|
46 |
//#define T2_TWI ((SYS_CLK *1300) /1000000) +1 // >1,3us |
|
47 |
//#define T4_TWI ((SYS_CLK * 600) /1000000) +1 // >0,6us |
|
48 |
|
|
49 |
|
|
50 |
//This may or may not make it faster. Uncomfirmed. But it works. |
|
51 |
#define T2_TWI 0.000001 |
|
52 |
#define T4_TWI 0.000001 |
|
53 |
|
|
54 |
// TWI STANDARD mode timing limits. SCL <= 100kHz |
|
55 |
//#define T2_TWI ((SYS_CLK *4700) /1000000) +1 // >4,7us |
|
56 |
//#define T4_TWI ((SYS_CLK *4000) /1000000) +1 // >4,0us |
|
57 |
|
|
58 |
//USI_TWI messages and flags and bit masks |
|
59 |
//#define SUCCESS 7 |
|
60 |
//#define MSG 0 |
|
61 |
/**************************************************************************** |
|
62 |
Bit and byte definitions |
|
63 |
****************************************************************************/ |
|
64 |
#define TWI_READ_BIT 0 // Bit position for R/W bit in "address byte". |
|
65 |
#define TWI_ADR_BITS 1 // Bit position for LSB of the slave address bits in the init byte. |
|
66 |
#define TWI_NACK_BIT 0 // Bit position for (N)ACK bit. |
|
67 |
|
|
68 |
#define USI_TWI_NO_DATA 0x00 // Transmission buffer is empty |
|
69 |
#define USI_TWI_DATA_OUT_OF_BOUND 0x01 // Transmission buffer is outside SRAM space |
|
70 |
#define USI_TWI_UE_START_CON 0x02 // Unexpected Start Condition |
|
71 |
#define USI_TWI_UE_STOP_CON 0x03 // Unexpected Stop Condition |
|
72 |
#define USI_TWI_UE_DATA_COL 0x04 // Unexpected Data Collision (arbitration) |
|
73 |
#define USI_TWI_NO_ACK_ON_DATA 0x05 // The slave did not acknowledge all data |
|
74 |
#define USI_TWI_NO_ACK_ON_ADDRESS 0x06 // The slave did not acknowledge the address |
|
75 |
#define USI_TWI_MISSING_START_CON 0x07 // Generated Start Condition not detected on bus |
|
76 |
#define USI_TWI_MISSING_STOP_CON 0x08 // Generated Stop Condition not detected on bus |
|
77 |
|
|
78 |
// Device dependant defines |
|
79 |
#define DDR_USI DDRB |
|
80 |
#define PORT_USI PORTB |
|
81 |
#define PIN_USI PINB |
|
82 |
#define PORT_USI_SDA PORTB0 |
|
83 |
#define PORT_USI_SCL PORTB2 |
|
84 |
#define PIN_USI_SDA PINB0 |
|
85 |
#define PIN_USI_SCL PINB2 |
|
86 |
|
|
87 |
// General defines |
|
88 |
#define TRUE 1 |
|
89 |
#define FALSE 0 |
|
90 |
|
|
91 |
//********** Prototypes **********// |
|
92 |
|
|
93 |
void USI_TWI_Master_Initialise( void ); |
|
94 |
unsigned char USI_TWI_Start_Transceiver_With_Data( unsigned char * , unsigned char ); |
|
95 |
unsigned char USI_TWI_Get_State_Info( void ); |
branches/autonomous_recharging/code/projects/autonomous_recharging/archs/homing stop/stop.c | ||
---|---|---|
1 | 1 |
#include<avr/io.h> |
2 |
#include <avr/interrupt.h> |
|
2 | 3 |
#include "i2c.h" |
3 | 4 |
|
4 | 5 |
#define LED1 PB4 //Green |
5 | 6 |
#define LED2 PB5 //Red |
6 | 7 |
|
8 |
// for i2c_byte coming from charge board |
|
9 |
//I2C Message Codes |
|
10 |
#define I2C_MSG_ACKNOWLEDGE 'A' |
|
11 |
#define I2C_MSG_BATTERY_CHARGING 'C' |
|
12 |
#define I2C_MSG_DATA 'D' |
|
13 |
#define I2C_MSG_CONTACT_ERROR 'E' |
|
14 |
#define I2C_MSG_BATTERY_FULL 'F' |
|
15 |
#define I2C_MSG_NO_CONTACT 'N' |
|
16 |
#define I2C_MSG_REQUEST_DATA 'R' |
|
17 |
#define I2C_MSG_GO_TO_SLEEP 'Y' |
|
18 |
#define I2C_MSG_ENTERING_SLEEP 'Z' |
|
19 |
#define I2C_MSG_HOMING 'H' |
|
20 |
|
|
21 |
|
|
22 |
#define SW0 PA6 |
|
23 |
#define HOMING_PIN PA7 |
|
24 |
|
|
25 |
uint8_t read_homing(void) |
|
26 |
{ |
|
27 |
uint8_t ret = PINA & _BV(HOMING_PIN); |
|
28 |
if(ret) |
|
29 |
PORTA |= _BV(PA3); |
|
30 |
else |
|
31 |
PORTA &= ~_BV(PA3); |
|
32 |
return ret; |
|
33 |
} |
|
34 |
|
|
35 |
uint8_t get_delay(void) |
|
36 |
{ |
|
37 |
uint8_t count = 0; |
|
38 |
|
|
39 |
PORTB|=_BV(LED2); |
|
40 |
while(read_homing()) |
|
41 |
{ |
|
42 |
delay_ms(1); |
|
43 |
count++; |
|
44 |
|
|
45 |
if (count >= 100) |
|
46 |
return 1; |
|
47 |
} //wait a beacon cycle to make sure we aren't starting the count in the middle of one |
|
48 |
PORTB&=~_BV(LED2); |
|
49 |
count = 0; |
|
50 |
PORTB|=_BV(LED1); |
|
51 |
while(!read_homing()) |
|
52 |
{ |
|
53 |
delay_ms(1); |
|
54 |
count++; |
|
55 |
if(count==255) |
|
56 |
return 2; |
|
57 |
} |
|
58 |
PORTB&=~_BV(LED1); |
|
59 |
|
|
60 |
/*RECH_PUTS("\n\rCount: "); |
|
61 |
RECH_PUTI(count); |
|
62 |
RECH_PUTC('.');*/ |
|
63 |
|
|
64 |
return count; |
|
65 |
} |
|
66 |
|
|
7 | 67 |
int main( void ) |
8 | 68 |
{ |
9 | 69 |
DDRB = _BV(PB0) | _BV(PB5) | _BV(PB4); |
... | ... | |
34 | 94 |
} |
35 | 95 |
else |
36 | 96 |
{ |
37 |
data[1]=I2C_MSG_NO_CONTACT; |
|
38 |
i2c_putpacket(0x01, data, 2); |
|
97 |
data[0]=I2C_MSG_NO_CONTACT; |
|
98 |
|
|
99 |
get_delay(); //reject the first reading //homing import stuff, uncomment this!!!!!! |
|
100 |
data[1]=I2C_MSG_HOMING; |
|
101 |
data[2]=get_delay(); |
|
102 |
i2c_putpacket(0x01, data, 3); |
|
39 | 103 |
} |
40 | 104 |
} |
41 | 105 |
|
branches/autonomous_recharging/code/projects/autonomous_recharging/archs/homing stop/USI_TWI_Slave.c | ||
---|---|---|
1 |
// This file has been prepared for Doxygen automatic documentation generation. |
|
2 |
/*! \file ******************************************************************** |
|
3 |
* |
|
4 |
* Atmel Corporation |
|
5 |
* |
|
6 |
* File : USI_TWI_Slave.c |
|
7 |
* Compiler : IAR EWAAVR 4.11A |
|
8 |
* Revision : $Revision: 1.14 $ |
|
9 |
* Date : $Date: Friday, December 09, 2005 17:25:38 UTC $ |
|
10 |
* Updated by : $Author: jtyssoe $ |
|
11 |
* |
|
12 |
* Support mail : avr@atmel.com |
|
13 |
* |
|
14 |
* Supported devices : All device with USI module can be used. |
|
15 |
* |
|
16 |
* AppNote : AVR312 - Using the USI module as a I2C slave |
|
17 |
* |
|
18 |
* Description : Functions for USI_TWI_receiver and USI_TWI_transmitter. |
|
19 |
* |
|
20 |
* |
|
21 |
****************************************************************************/ |
|
22 |
|
|
23 |
#ifndef _USI_TWI_SLAVE_H |
|
24 |
#define _USI_TWI_SLAVE_H |
|
25 |
|
|
26 |
#include <avr/io.h> |
|
27 |
#include <avr/interrupt.h> |
|
28 |
#include "USI_TWI_Slave.h" |
|
29 |
|
|
30 |
/*! Static Variables */ |
|
31 |
|
|
32 |
static unsigned char TWI_slaveAddress; |
|
33 |
static volatile unsigned char USI_TWI_Overflow_State; |
|
34 |
|
|
35 |
/*! Local variables */ |
|
36 |
static uint8_t TWI_RxBuf[TWI_RX_BUFFER_SIZE]; |
|
37 |
static volatile uint8_t TWI_RxHead; |
|
38 |
static volatile uint8_t TWI_RxTail; |
|
39 |
|
|
40 |
static uint8_t TWI_TxBuf[TWI_TX_BUFFER_SIZE]; |
|
41 |
static volatile uint8_t TWI_TxHead; |
|
42 |
static volatile uint8_t TWI_TxTail; |
|
43 |
|
|
44 |
/*! \brief Flushes the TWI buffers |
|
45 |
*/ |
|
46 |
void Flush_TWI_Buffers(void) |
|
47 |
{ |
|
48 |
TWI_RxTail = 0; |
|
49 |
TWI_RxHead = 0; |
|
50 |
TWI_TxTail = 0; |
|
51 |
TWI_TxHead = 0; |
|
52 |
} |
|
53 |
|
|
54 |
//********** USI_TWI functions **********// |
|
55 |
|
|
56 |
/*! \brief |
|
57 |
* Initialise USI for TWI Slave mode. |
|
58 |
*/ |
|
59 |
void USI_TWI_Slave_Initialise( unsigned char TWI_ownAddress ) |
|
60 |
{ |
|
61 |
Flush_TWI_Buffers(); |
|
62 |
|
|
63 |
TWI_slaveAddress = TWI_ownAddress; |
|
64 |
|
|
65 |
PORT_USI |= (1<<PORT_USI_SCL); // Set SCL high |
|
66 |
PORT_USI |= (1<<PORT_USI_SDA); // Set SDA high |
|
67 |
DDR_USI |= (1<<PORT_USI_SCL); // Set SCL as output |
|
68 |
DDR_USI &= ~(1<<PORT_USI_SDA); // Set SDA as input |
|
69 |
USICR = (1<<USISIE)|(0<<USIOIE)| // Enable Start Condition Interrupt. Disable Overflow Interrupt. |
|
70 |
(1<<USIWM1)|(0<<USIWM0)| // Set USI in Two-wire mode. No USI Counter overflow prior |
|
71 |
// to first Start Condition (potentail failure) |
|
72 |
(1<<USICS1)|(0<<USICS0)|(0<<USICLK)| // Shift Register Clock Source = External, positive edge |
|
73 |
(0<<USITC); |
|
74 |
USISR = 0xF0; // Clear all flags and reset overflow counter |
|
75 |
} |
|
76 |
|
|
77 |
|
|
78 |
/*! \brief Puts data in the transmission buffer, Waits if buffer is full. |
|
79 |
*/ |
|
80 |
void USI_TWI_Transmit_Byte( unsigned char data ) |
|
81 |
{ |
|
82 |
unsigned char tmphead; |
|
83 |
|
|
84 |
tmphead = ( TWI_TxHead + 1 ) & TWI_TX_BUFFER_MASK; // Calculate buffer index. |
|
85 |
while ( tmphead == TWI_TxTail ); // Wait for free space in buffer. |
|
86 |
TWI_TxBuf[tmphead] = data; // Store data in buffer. |
|
87 |
TWI_TxHead = tmphead; // Store new index. |
|
88 |
} |
|
89 |
|
|
90 |
/*! \brief Returns a byte from the receive buffer. Waits if buffer is empty. |
|
91 |
*/ |
|
92 |
unsigned char USI_TWI_Receive_Byte( void ) |
|
93 |
{ |
|
94 |
unsigned char tmptail; |
|
95 |
unsigned char tmpRxTail; // Temporary variable to store volatile |
|
96 |
tmpRxTail = TWI_RxTail; // Not necessary, but prevents warnings |
|
97 |
while ( TWI_RxHead == tmpRxTail ); |
|
98 |
tmptail = ( TWI_RxTail + 1 ) & TWI_RX_BUFFER_MASK; // Calculate buffer index |
|
99 |
TWI_RxTail = tmptail; // Store new index |
|
100 |
return TWI_RxBuf[tmptail]; // Return data from the buffer. |
|
101 |
} |
|
102 |
|
|
103 |
/*! \brief Check if there is data in the receive buffer. |
|
104 |
*/ |
|
105 |
unsigned char USI_TWI_Data_In_Receive_Buffer( void ) |
|
106 |
{ |
|
107 |
unsigned char tmpRxTail; // Temporary variable to store volatile |
|
108 |
tmpRxTail = TWI_RxTail; // Not necessary, but prevents warnings |
|
109 |
return ( TWI_RxHead != tmpRxTail ); // Return 0 (FALSE) if the receive buffer is empty. |
|
110 |
} |
|
111 |
|
|
112 |
/*! \brief Usi start condition ISR |
|
113 |
* Detects the USI_TWI Start Condition and intialises the USI |
|
114 |
* for reception of the "TWI Address" packet. |
|
115 |
*/ |
|
116 |
ISR(USI_START_vect) { |
|
117 |
|
|
118 |
unsigned char tmpUSISR; // Temporary variable to store volatile |
|
119 |
tmpUSISR = USISR; // Not necessary, but prevents warnings |
|
120 |
// Set default starting conditions for new TWI package |
|
121 |
USI_TWI_Overflow_State = USI_SLAVE_CHECK_ADDRESS; |
|
122 |
DDR_USI &= ~(1<<PORT_USI_SDA); // Set SDA as input |
|
123 |
while ( (PIN_USI & (1<<PORT_USI_SCL)) & !(tmpUSISR & (1<<USIPF)) ); // Wait for SCL to go low to ensure the "Start Condition" has completed. |
|
124 |
// If a Stop condition arises then leave the interrupt to prevent waiting forever. |
|
125 |
USICR = (1<<USISIE)|(1<<USIOIE)| // Enable Overflow and Start Condition Interrupt. (Keep StartCondInt to detect RESTART) |
|
126 |
(1<<USIWM1)|(1<<USIWM0)| // Set USI in Two-wire mode. |
|
127 |
(1<<USICS1)|(0<<USICS0)|(0<<USICLK)| // Shift Register Clock Source = External, positive edge |
|
128 |
(0<<USITC); |
|
129 |
USISR = (1<<USI_START_COND_INT)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| // Clear flags |
|
130 |
(0x0<<USICNT0); // Set USI to sample 8 bits i.e. count 16 external pin toggles. |
|
131 |
} |
|
132 |
|
|
133 |
|
|
134 |
/*! \brief USI counter overflow ISR |
|
135 |
* Handels all the comunication. Is disabled only when waiting |
|
136 |
* for new Start Condition. |
|
137 |
*/ |
|
138 |
ISR(USI_OVF_vect) { |
|
139 |
|
|
140 |
unsigned char tmpTxTail; // Temporary variables to store volatiles |
|
141 |
unsigned char tmpUSIDR; |
|
142 |
|
|
143 |
|
|
144 |
switch (USI_TWI_Overflow_State) |
|
145 |
{ |
|
146 |
// ---------- Address mode ---------- |
|
147 |
// Check address and send ACK (and next USI_SLAVE_SEND_DATA) if OK, else reset USI. |
|
148 |
case USI_SLAVE_CHECK_ADDRESS: |
|
149 |
if ((USIDR == 0) || (( USIDR>>1 ) == TWI_slaveAddress)) |
|
150 |
{ |
|
151 |
if ( USIDR & 0x01 ) |
|
152 |
USI_TWI_Overflow_State = USI_SLAVE_SEND_DATA; |
|
153 |
else |
|
154 |
USI_TWI_Overflow_State = USI_SLAVE_REQUEST_DATA; |
|
155 |
SET_USI_TO_SEND_ACK(); |
|
156 |
} |
|
157 |
else |
|
158 |
{ |
|
159 |
SET_USI_TO_TWI_START_CONDITION_MODE(); |
|
160 |
} |
|
161 |
break; |
|
162 |
|
|
163 |
// ----- Master write data mode ------ |
|
164 |
// Check reply and goto USI_SLAVE_SEND_DATA if OK, else reset USI. |
|
165 |
case USI_SLAVE_CHECK_REPLY_FROM_SEND_DATA: |
|
166 |
if ( USIDR ) // If NACK, the master does not want more data. |
|
167 |
{ |
|
168 |
SET_USI_TO_TWI_START_CONDITION_MODE(); |
|
169 |
return; |
|
170 |
} |
|
171 |
// From here we just drop straight into USI_SLAVE_SEND_DATA if the master sent an ACK |
|
172 |
|
|
173 |
// Copy data from buffer to USIDR and set USI to shift byte. Next USI_SLAVE_REQUEST_REPLY_FROM_SEND_DATA |
|
174 |
case USI_SLAVE_SEND_DATA: |
|
175 |
|
|
176 |
// Get data from Buffer |
|
177 |
tmpTxTail = TWI_TxTail; // Not necessary, but prevents warnings |
|
178 |
if ( TWI_TxHead != tmpTxTail ) |
|
179 |
{ |
|
180 |
TWI_TxTail = ( TWI_TxTail + 1 ) & TWI_TX_BUFFER_MASK; |
|
181 |
USIDR = TWI_TxBuf[TWI_TxTail]; |
|
182 |
} |
|
183 |
else // If the buffer is empty then: |
|
184 |
{ |
|
185 |
SET_USI_TO_TWI_START_CONDITION_MODE(); |
|
186 |
return; |
|
187 |
} |
|
188 |
USI_TWI_Overflow_State = USI_SLAVE_REQUEST_REPLY_FROM_SEND_DATA; |
|
189 |
SET_USI_TO_SEND_DATA(); |
|
190 |
break; |
|
191 |
|
|
192 |
// Set USI to sample reply from master. Next USI_SLAVE_CHECK_REPLY_FROM_SEND_DATA |
|
193 |
case USI_SLAVE_REQUEST_REPLY_FROM_SEND_DATA: |
|
194 |
USI_TWI_Overflow_State = USI_SLAVE_CHECK_REPLY_FROM_SEND_DATA; |
|
195 |
SET_USI_TO_READ_ACK(); |
|
196 |
break; |
|
197 |
|
|
198 |
// ----- Master read data mode ------ |
|
199 |
// Set USI to sample data from master. Next USI_SLAVE_GET_DATA_AND_SEND_ACK. |
|
200 |
case USI_SLAVE_REQUEST_DATA: |
|
201 |
USI_TWI_Overflow_State = USI_SLAVE_GET_DATA_AND_SEND_ACK; |
|
202 |
SET_USI_TO_READ_DATA(); |
|
203 |
break; |
|
204 |
|
|
205 |
// Copy data from USIDR and send ACK. Next USI_SLAVE_REQUEST_DATA |
|
206 |
case USI_SLAVE_GET_DATA_AND_SEND_ACK: |
|
207 |
// Put data into Buffer |
|
208 |
tmpUSIDR = USIDR; // Not necessary, but prevents warnings |
|
209 |
TWI_RxHead = ( TWI_RxHead + 1 ) & TWI_RX_BUFFER_MASK; |
|
210 |
TWI_RxBuf[TWI_RxHead] = tmpUSIDR; |
|
211 |
|
|
212 |
USI_TWI_Overflow_State = USI_SLAVE_REQUEST_DATA; |
|
213 |
SET_USI_TO_SEND_ACK(); |
|
214 |
break; |
|
215 |
} |
|
216 |
} |
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#endif |
branches/autonomous_recharging/code/projects/autonomous_recharging/archs/homing stop/i2c.c | ||
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/* I2C.c |
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I2C Communication |
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Problem switching into slave mode. So never run as a slave otherwise you will never be able |
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to speak again (unless a master tells you to). |
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*/ |
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#include "i2c.h" |
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/* |
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int main(void) { |
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i2c_test(); |
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} |
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*/ |
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//Call this to start I2C up |
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void i2c_init(void) { |
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//Start off in slave mode so you can catch any data that comes your way |
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//USI_TWI_Slave_Initialise(0x02); |
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//Can't ever be a slave otherwise you will die. Stay as master and never give it up. |
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USI_TWI_Master_Initialise(); |
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} |
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//Call this to send a packet. *data is a char array of data_size. Make sure you put in data_size or we won't send |
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//everything. |
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//Note, mainboard is addr = 0x01. |
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void i2c_putpacket(char addr, char *data, char data_size) { |
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//The packet that we will transmit over I2C |
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unsigned char packet[data_size + 1]; |
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//First byte is the destination address + R/W (R = 1, W = 0) |
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packet[0] = addr << 1; //Shift the address over 1 bit, LSB is 0 which means write |
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//Put data into packet |
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for (int i = 0; i < data_size; i++) { |
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packet[i+1] = data[i]; |
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} |
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//Send packet. Will open line, transmit, and close line. |
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USI_TWI_Start_Transceiver_With_Data(packet, (data_size + 1)); |
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} |
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int i2c_getpacket(char *c) { |
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if (USI_TWI_Data_In_Receive_Buffer()) { |
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*c = USI_TWI_Receive_Byte(); |
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return 0; |
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} else{ |
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return -1; |
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} |
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} |
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void delay_ms(int ms) |
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{ |
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for(; ms > 15; ms-=15) |
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_delay_ms(15); |
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_delay_ms(ms); |
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} |
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// Note this will fail. You need to fix the switch from slave -> master before it will succeed. |
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void i2c_test(void) { |
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char datatx[] = {'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z'}; |
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char datarx; |
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DDRA = _BV(PA3) | _BV(PA4) | _BV(PA5) | _BV(PA6) | _BV(PA7); |
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PORTA = 0; |
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PORTA |= _BV(PA3); |
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//delay_ms(1000); |
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sei(); |
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i2c_init(); |
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while(1) { |
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delay_ms(1000); |
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i2c_putpacket(0x01, datatx, 26); |
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} |
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/* |
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while(1) { |
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i2c_getpacket(&datarx); |
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switch (datarx) { |
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case 'a': |
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PORTA |= _BV(PA4); |
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break; |
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case 'b': |
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PORTA |= _BV(PA5); |
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break; |
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case 'c': |
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PORTA |= _BV(PA6); |
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break; |
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case 'd': |
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PORTA |= _BV(PA7); |
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break; |
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} |
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if (datarx == 'd') |
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break; |
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} |
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PORTA = 0; |
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//PORTA |= _BV(PA5); |
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delay_ms(1000); |
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i2c_putpacket(0x01, datatx, 26); |
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*/ |
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} |
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