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/*****************************************************************************
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*
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* Atmel Corporation
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*
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* File              : USI_TWI_Master.h
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* Compiler          : IAR EWAAVR 2.28a/3.10a
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* Revision          : $Revision: 1.11 $
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* Date              : $Date: Tuesday, September 13, 2005 09:09:36 UTC $
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* Updated by        : $Author: jtyssoe $
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*
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* Support mail      : avr@atmel.com
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*
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* Supported devices : All device with USI module can be used.
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*                     The example is written for the ATmega169, ATtiny26 and ATtiny2313
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*
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* AppNote           : AVR310 - Using the USI module as a TWI Master
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*
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* Description       : This is an implementation of an TWI master using
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*                     the USI module as basis. The implementation assumes the AVR to
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*                     be the only TWI master in the system and can therefore not be
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*                     used in a multi-master system.
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* Usage             : Initialize the USI module by calling the USI_TWI_Master_Initialise()
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*                     function. Hence messages/data are transceived on the bus using
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*                     the USI_TWI_Start_Transceiver_With_Data() function. If the transceiver
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*                     returns with a fail, then use USI_TWI_Get_Status_Info to evaluate the
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*                     couse of the failure.
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*
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****************************************************************************/
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//********** Defines **********//
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// Defines controlling timing limits
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//#define TWI_FAST_MODE
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//#define SYS_CLK   4000.0  // [kHz]
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//Note, this is only a variable that determines how long to delay between
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// individual bits of I2C send. This has been tested down to 1MHz and it works.
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// It is possible that even slower speeds can be obtained.
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#define SYS_CLK     1.0 // [mHz]
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// TWI FAST mode timing limits. SCL = 100-400kHz
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//#define T2_TWI    ((SYS_CLK *1300) /1000000) +1 // >1,3us
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//#define T4_TWI    ((SYS_CLK * 600) /1000000) +1 // >0,6us
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//This may or may not make it faster. Uncomfirmed. But it works.
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#define T2_TWI 0.000001
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#define T4_TWI 0.000001
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// TWI STANDARD mode timing limits. SCL <= 100kHz
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//#define T2_TWI    ((SYS_CLK *4700) /1000000) +1 // >4,7us
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//#define T4_TWI    ((SYS_CLK *4000) /1000000) +1 // >4,0us
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//USI_TWI messages and flags and bit masks
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//#define SUCCESS   7
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//#define MSG       0
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/****************************************************************************
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  Bit and byte definitions
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****************************************************************************/
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#define TWI_READ_BIT  0       // Bit position for R/W bit in "address byte".
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#define TWI_ADR_BITS  1       // Bit position for LSB of the slave address bits in the init byte.
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#define TWI_NACK_BIT  0       // Bit position for (N)ACK bit.
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#define USI_TWI_NO_DATA             0x00  // Transmission buffer is empty
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#define USI_TWI_DATA_OUT_OF_BOUND   0x01  // Transmission buffer is outside SRAM space
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#define USI_TWI_UE_START_CON        0x02  // Unexpected Start Condition
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#define USI_TWI_UE_STOP_CON         0x03  // Unexpected Stop Condition
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#define USI_TWI_UE_DATA_COL         0x04  // Unexpected Data Collision (arbitration)
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#define USI_TWI_NO_ACK_ON_DATA      0x05  // The slave did not acknowledge  all data
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#define USI_TWI_NO_ACK_ON_ADDRESS   0x06  // The slave did not acknowledge  the address
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#define USI_TWI_MISSING_START_CON   0x07  // Generated Start Condition not detected on bus
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#define USI_TWI_MISSING_STOP_CON    0x08  // Generated Stop Condition not detected on bus
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// Device dependant defines
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#define DDR_USI             DDRB
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#define PORT_USI            PORTB
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#define PIN_USI             PINB
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#define PORT_USI_SDA        PORTB0
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#define PORT_USI_SCL        PORTB2
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#define PIN_USI_SDA         PINB0
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#define PIN_USI_SCL         PINB2
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// General defines
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#define TRUE  1
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#define FALSE 0
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//********** Prototypes **********//
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void USI_TWI_Master_Initialise( void );
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unsigned char USI_TWI_Start_Transceiver_With_Data( unsigned char * , unsigned char );
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unsigned char USI_TWI_Get_State_Info( void );