root / branches / autonomous_recharging / code / projects / autonomous_recharging / archs / I2c test / USI_TWI_Master.h @ 355
History | View | Annotate | Download (4.01 KB)
1 | 355 | bneuman | |
---|---|---|---|
2 | |||
3 | |||
4 | /*****************************************************************************
|
||
5 | *
|
||
6 | * Atmel Corporation
|
||
7 | *
|
||
8 | * File : USI_TWI_Master.h
|
||
9 | * Compiler : IAR EWAAVR 2.28a/3.10a
|
||
10 | * Revision : $Revision: 1.11 $
|
||
11 | * Date : $Date: Tuesday, September 13, 2005 09:09:36 UTC $
|
||
12 | * Updated by : $Author: jtyssoe $
|
||
13 | *
|
||
14 | * Support mail : avr@atmel.com
|
||
15 | *
|
||
16 | * Supported devices : All device with USI module can be used.
|
||
17 | * The example is written for the ATmega169, ATtiny26 and ATtiny2313
|
||
18 | *
|
||
19 | * AppNote : AVR310 - Using the USI module as a TWI Master
|
||
20 | *
|
||
21 | * Description : This is an implementation of an TWI master using
|
||
22 | * the USI module as basis. The implementation assumes the AVR to
|
||
23 | * be the only TWI master in the system and can therefore not be
|
||
24 | * used in a multi-master system.
|
||
25 | * Usage : Initialize the USI module by calling the USI_TWI_Master_Initialise()
|
||
26 | * function. Hence messages/data are transceived on the bus using
|
||
27 | * the USI_TWI_Start_Transceiver_With_Data() function. If the transceiver
|
||
28 | * returns with a fail, then use USI_TWI_Get_Status_Info to evaluate the
|
||
29 | * couse of the failure.
|
||
30 | *
|
||
31 | ****************************************************************************/
|
||
32 | |||
33 | //********** Defines **********//
|
||
34 | |||
35 | // Defines controlling timing limits
|
||
36 | //#define TWI_FAST_MODE
|
||
37 | |||
38 | //#define SYS_CLK 4000.0 // [kHz]
|
||
39 | |||
40 | //Note, this is only a variable that determines how long to delay between
|
||
41 | // individual bits of I2C send. This has been tested down to 1MHz and it works.
|
||
42 | // It is possible that even slower speeds can be obtained.
|
||
43 | #define SYS_CLK 1.0 // [mHz] |
||
44 | |||
45 | // TWI FAST mode timing limits. SCL = 100-400kHz
|
||
46 | //#define T2_TWI ((SYS_CLK *1300) /1000000) +1 // >1,3us
|
||
47 | //#define T4_TWI ((SYS_CLK * 600) /1000000) +1 // >0,6us
|
||
48 | |||
49 | |||
50 | //This may or may not make it faster. Uncomfirmed. But it works.
|
||
51 | #define T2_TWI 0.000001 |
||
52 | #define T4_TWI 0.000001 |
||
53 | |||
54 | // TWI STANDARD mode timing limits. SCL <= 100kHz
|
||
55 | //#define T2_TWI ((SYS_CLK *4700) /1000000) +1 // >4,7us
|
||
56 | //#define T4_TWI ((SYS_CLK *4000) /1000000) +1 // >4,0us
|
||
57 | |||
58 | //USI_TWI messages and flags and bit masks
|
||
59 | //#define SUCCESS 7
|
||
60 | //#define MSG 0
|
||
61 | /****************************************************************************
|
||
62 | Bit and byte definitions
|
||
63 | ****************************************************************************/
|
||
64 | #define TWI_READ_BIT 0 // Bit position for R/W bit in "address byte". |
||
65 | #define TWI_ADR_BITS 1 // Bit position for LSB of the slave address bits in the init byte. |
||
66 | #define TWI_NACK_BIT 0 // Bit position for (N)ACK bit. |
||
67 | |||
68 | #define USI_TWI_NO_DATA 0x00 // Transmission buffer is empty |
||
69 | #define USI_TWI_DATA_OUT_OF_BOUND 0x01 // Transmission buffer is outside SRAM space |
||
70 | #define USI_TWI_UE_START_CON 0x02 // Unexpected Start Condition |
||
71 | #define USI_TWI_UE_STOP_CON 0x03 // Unexpected Stop Condition |
||
72 | #define USI_TWI_UE_DATA_COL 0x04 // Unexpected Data Collision (arbitration) |
||
73 | #define USI_TWI_NO_ACK_ON_DATA 0x05 // The slave did not acknowledge all data |
||
74 | #define USI_TWI_NO_ACK_ON_ADDRESS 0x06 // The slave did not acknowledge the address |
||
75 | #define USI_TWI_MISSING_START_CON 0x07 // Generated Start Condition not detected on bus |
||
76 | #define USI_TWI_MISSING_STOP_CON 0x08 // Generated Stop Condition not detected on bus |
||
77 | |||
78 | // Device dependant defines
|
||
79 | #define DDR_USI DDRB
|
||
80 | #define PORT_USI PORTB
|
||
81 | #define PIN_USI PINB
|
||
82 | #define PORT_USI_SDA PORTB0
|
||
83 | #define PORT_USI_SCL PORTB2
|
||
84 | #define PIN_USI_SDA PINB0
|
||
85 | #define PIN_USI_SCL PINB2
|
||
86 | |||
87 | // General defines
|
||
88 | #define TRUE 1 |
||
89 | #define FALSE 0 |
||
90 | |||
91 | //********** Prototypes **********//
|
||
92 | |||
93 | void USI_TWI_Master_Initialise( void ); |
||
94 | unsigned char USI_TWI_Start_Transceiver_With_Data( unsigned char * , unsigned char ); |
||
95 | unsigned char USI_TWI_Get_State_Info( void ); |