root / prex-0.9.0 / bsp / hal / arm / include / cpu.h @ 03e9c04a
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/*-
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* Copyright (c) 2005-2008, Kohsuke Ohtani
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _ARM_CPU_H
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#define _ARM_CPU_H
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/*
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* Processor Status Register
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*/
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#define PSR_MODE 0x0000001f |
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#define PSR_USR_MODE 0x00000010 |
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#define PSR_FIQ_MODE 0x00000011 |
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#define PSR_IRQ_MODE 0x00000012 |
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#define PSR_SVC_MODE 0x00000013 |
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#define PSR_ABT_MODE 0x00000017 |
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#define PSR_UND_MODE 0x0000001b |
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#define PSR_SYS_MODE 0x0000001f |
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#define PSR_THUMB 0x00000020 |
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#define PSR_INT_MASK 0x000000c0 |
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#define PSR_FIQ_DIS 0x00000040 |
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#define PSR_IRQ_DIS 0x00000080 |
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#ifdef __gba__
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#define PSR_APP_MODE PSR_SYS_MODE
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#else
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#define PSR_APP_MODE PSR_USR_MODE
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#endif
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/*
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* Contorl register CP15 register 1
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*/
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#define CTL_MMU 0x000000001 /* M: MMU/Protection unit enable */ |
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#define CTL_AFLT 0x000000002 /* A: Alignment fault enable */ |
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#define CTL_CACHE 0x000000004 /* C: Cache enable */ |
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#define CTL_WBUF 0x000000008 /* W: Write buffer enable */ |
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#define CTL_32BP 0x000000010 /* P: 32-bit exception handlers */ |
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#define CTL_32BD 0x000000020 /* D: 32-bit addressing */ |
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#define CTL_LABT 0x000000040 /* L: Late abort enable */ |
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#define CTL_BIGEND 0x000000080 /* B: Big-endian mode */ |
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#define CTL_SYSP 0x000000100 /* S: System protection bit */ |
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#define CTL_ROMP 0x000000200 /* R: ROM protection bit */ |
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#define CTL_BPRD 0x000000800 /* Z: Branch prediction enable */ |
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#define CTL_ICACHE 0x000001000 /* I: Instruction cache enable */ |
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#define CTL_HIVEC 0x000002000 /* V: Vector relocation */ |
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#define CTL_DEFAULT (CTL_32BP | CTL_32BD | CTL_LABT)
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#ifndef __ASSEMBLY__
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__BEGIN_DECLS |
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void cpu_init(void); |
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__END_DECLS |
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#endif /* !__ASSEMBLY__ */ |
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#endif /* !_ARM_CPU_H */ |