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/*-
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 * Copyright (c) 2008-2009, Kohsuke Ohtani
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * 1. Redistributions of source code must retain the above copyright
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 *    notice, this list of conditions and the following disclaimer.
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 * 2. Redistributions in binary form must reproduce the above copyright
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 *    notice, this list of conditions and the following disclaimer in the
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 *    documentation and/or other materials provided with the distribution.
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 * 3. Neither the name of the author nor the names of any co-contributors
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 *    may be used to endorse or promote products derived from this software
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 *    without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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 * SUCH DAMAGE.
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 */
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/*
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 * mmu.c - memory management unit support routines
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 */
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/*
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 * This module provides virtual/physical address translation for
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 * ARM MMU. This kernel will do only page level translation
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 * and protection and it does not use ARM protection domain.
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 */
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#include <machine/syspage.h>
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#include <kernel.h>
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#include <page.h>
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#include <mmu.h>
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#include <cpu.h>
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#include <cpufunc.h>
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#define L1TBL_MASK        (L1TBL_SIZE - 1)
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#define PGD_ALIGN(n)        ((((paddr_t)(n)) + L1TBL_MASK) & ~L1TBL_MASK)
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/*
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 * Boot page directory.
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 * This works as a template for all page directory in the system.
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 */
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static pgd_t boot_pgd = (pgd_t)BOOT_PGD;
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/*
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 * Allocate pgd
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 *
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 * The page directory for ARM must be aligned in 16K bytes
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 * boundary. So, we allocates 32K bytes first, and use
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 * 16K-aligned area in it.
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 */
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static paddr_t
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alloc_pgd(void)
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{
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        paddr_t pg, pgd;
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        size_t gap;
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        /* Allocate 32K first. */
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        if ((pg = page_alloc(L1TBL_SIZE * 2)) == 0)
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                return 0;
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        /* Find 16K aligned pointer */
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        pgd = PGD_ALIGN(pg);
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        /* Release un-needed area */
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        gap = (size_t)(pgd - pg);
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        if (gap != 0)
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                page_free(pg, gap);
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        page_free((paddr_t)(pgd + L1TBL_SIZE), (size_t)(L1TBL_SIZE - gap));
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        return pgd;
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}
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/*
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 * Map physical memory range into virtual address
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 *
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 * Returns 0 on success, or ENOMEM on failure.
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 *
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 * Map type can be one of the following type.
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 *   PG_UNMAP  - Remove mapping
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 *   PG_READ   - Read only mapping
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 *   PG_WRITE  - Read/write allowed
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 *   PG_SYSTEM - Kernel page
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 *   PG_IO     - I/O memory
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 *
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 * Setup the appropriate page tables for mapping. If there is no
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 * page table for the specified address, new page table is
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 * allocated.
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 *
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 * This routine does not return any error even if the specified
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 * address has been already mapped to other physical address.
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 * In this case, it will just override the existing mapping.
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 *
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 * In order to unmap the page, pg_type is specified as 0.  But,
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 * the page tables are not released even if there is no valid
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 * page entry in it. All page tables are released when mmu_delmap()
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 * is called when task is terminated.
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 */
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int
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mmu_map(pgd_t pgd, paddr_t pa, vaddr_t va, size_t size, int type)
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{
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        uint32_t pte_flag = 0;
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        pte_t pte;
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        paddr_t pg;        /* page */
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        pa = round_page(pa);
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        va = round_page(va);
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        size = trunc_page(size);
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        /*
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         * Set page flag
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         */
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        switch (type) {
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        case PG_UNMAP:
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                pte_flag = 0;
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                break;
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        case PG_READ:
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                pte_flag = (uint32_t)(PTE_PRESENT | PTE_WBUF | PTE_CACHE |
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                                      PTE_USER_RO);
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                break;
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        case PG_WRITE:
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                pte_flag = (uint32_t)(PTE_PRESENT | PTE_WBUF | PTE_CACHE |
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                                      PTE_USER_RW);
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                break;
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        case PG_SYSTEM:
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                pte_flag = (uint32_t)(PTE_PRESENT | PTE_WBUF | PTE_CACHE |
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                                      PTE_SYSTEM);
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                break;
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        case PG_IOMEM:
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                pte_flag = (uint32_t)(PTE_PRESENT | PTE_SYSTEM);
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                break;
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        default:
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                panic("mmu_map");
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        }
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        /*
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         * Map all pages
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         */
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        flush_tlb();
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        while (size > 0) {
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                if (pte_present(pgd, va)) {
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                        /* Page table already exists for the address */
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                        pte = vtopte(pgd, va);
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                } else {
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                        ASSERT(pte_flag != 0);
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                        if ((pg = page_alloc(L2TBL_SIZE)) == 0) {
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                                DPRINTF(("Error: MMU mapping failed\n"));
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                                return ENOMEM;
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                        }
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                        pgd[PAGE_DIR(va)] = (uint32_t)pg | PDE_PRESENT;
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                        pte = (pte_t)ptokv(pg);
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                        memset(pte, 0, L2TBL_SIZE);
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                }
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                /* Set new entry into page table */
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                pte[PAGE_TABLE(va)] = (uint32_t)pa | pte_flag;
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                /* Process next page */
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                pa += PAGE_SIZE;
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                va += PAGE_SIZE;
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                size -= PAGE_SIZE;
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        }
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        flush_tlb();
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        return 0;
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}
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/*
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 * Create new page map.
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 *
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 * Returns a page directory on success, or NULL on failure.  This
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 * routine is called when new task is created. All page map must
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 * have the same kernel page table in it. So, the kernel page
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 * tables are copied to newly created map.
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 */
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pgd_t
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mmu_newmap(void)
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{
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        paddr_t pg;
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        pgd_t pgd;
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        int i;
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        if ((pg = alloc_pgd()) == 0)
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                return NO_PGD;
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        pgd = (pgd_t)ptokv(pg);
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        memset(pgd, 0, L1TBL_SIZE);
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        /* Copy kernel page tables */
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        i = PAGE_DIR(KERNBASE);
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        memcpy(&pgd[i], &boot_pgd[i], (size_t)(L1TBL_SIZE - i * 4));
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        /* Map vector page (address 0) */
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        mmu_map(pgd, 0, 0, PAGE_SIZE, PG_SYSTEM);
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        return pgd;
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}
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/*
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 * Terminate all page mapping.
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 */
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void
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mmu_terminate(pgd_t pgd)
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{
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        int i;
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        pte_t pte;
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        flush_tlb();
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        /* Release all user page table */
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        for (i = 0; i < PAGE_DIR(KERNBASE); i++) {
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                pte = (pte_t)pgd[i];
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                if (pte != 0)
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                        page_free(((paddr_t)pte & PTE_ADDRESS),
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                                  L2TBL_SIZE);
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        }
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        /* Release page directory */
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        page_free(kvtop(pgd), L1TBL_SIZE);
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}
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/*
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 * Switch to new page directory
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 *
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 * This is called when context is switched.
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 * Whole TLB/cache must be flushed after loading
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 * TLTB register
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 */
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void
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mmu_switch(pgd_t pgd)
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{
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        paddr_t phys = kvtop(pgd);
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        if (phys != get_ttb())
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                switch_ttb(phys);
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}
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/*
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 * Returns the physical address for the specified virtual address.
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 * This routine checks if the virtual area actually exist.
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 * It returns NULL if at least one page is not mapped.
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 */
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paddr_t
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mmu_extract(pgd_t pgd, vaddr_t virt, size_t size)
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{
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        pte_t pte;
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        vaddr_t start, end, pg;
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        paddr_t pa;
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        start = trunc_page(virt);
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        end = trunc_page(virt + size - 1);
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        /* Check all pages exist */
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        for (pg = start; pg <= end; pg += PAGE_SIZE) {
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                if (!pte_present(pgd, pg))
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                        return 0;
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                pte = vtopte(pgd, pg);
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                if (!page_present(pte, pg))
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                        return 0;
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        }
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        /* Get physical address */
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        pte = vtopte(pgd, start);
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        pa = (paddr_t)ptetopg(pte, start);
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        return pa + (paddr_t)(virt - start);
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}
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/*
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 * Map I/O memory for diagnostic device at very early stage.
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 */
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void
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mmu_premap(paddr_t phys, vaddr_t virt)
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{
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        pte_t pte = (pte_t)BOOT_PTE1;
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        memset(pte, 0, L2TBL_SIZE);
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        boot_pgd[PAGE_DIR(virt)] = (uint32_t)kvtop(pte) | PDE_PRESENT;
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        pte[PAGE_TABLE(virt)] = (uint32_t)phys | PTE_PRESENT | PTE_SYSTEM;
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        flush_tlb();
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}
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/*
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 * Initialize mmu
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 *
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 * Paging is already enabled in locore.S. And, physical address
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 * 0-4M has been already mapped into kernel space in locore.S.
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 * Now, all physical memory is mapped into kernel virtual address
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 * as straight 1:1 mapping. User mode access is not allowed for
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 * these kernel pages.
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 * page_init() must be called before calling this routine.
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 */
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void
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mmu_init(struct mmumap *mmumap_table)
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{
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        struct mmumap *map;
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        int map_type = 0;
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        for (map = mmumap_table; map->type != 0; map++) {
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                switch (map->type) {
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                case VMT_RAM:
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                case VMT_ROM:
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                case VMT_DMA:
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                        map_type = PG_SYSTEM;
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                        break;
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                case VMT_IO:
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                        map_type = PG_IOMEM;
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                        break;
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                }
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                if (mmu_map(boot_pgd, map->phys, map->virt,
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                            map->size, map_type))
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                        panic("mmu_init");
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        }
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        /*
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         * Map vector page.
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         */
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        if (mmu_map(boot_pgd, 0, CONFIG_ARM_VECTORS, PAGE_SIZE, PG_SYSTEM))
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                panic("mmu_init");
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}