root / prex-0.9.0 / bsp / hal / arm / include / cpu.h @ 03e9c04a
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1 | 03e9c04a | Brad Neuman | /*-
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2 | * Copyright (c) 2005-2008, Kohsuke Ohtani
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3 | * All rights reserved.
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4 | *
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5 | * Redistribution and use in source and binary forms, with or without
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6 | * modification, are permitted provided that the following conditions
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7 | * are met:
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8 | * 1. Redistributions of source code must retain the above copyright
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9 | * notice, this list of conditions and the following disclaimer.
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10 | * 2. Redistributions in binary form must reproduce the above copyright
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11 | * notice, this list of conditions and the following disclaimer in the
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12 | * documentation and/or other materials provided with the distribution.
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13 | * 3. Neither the name of the author nor the names of any co-contributors
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14 | * may be used to endorse or promote products derived from this software
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15 | * without specific prior written permission.
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16 | *
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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27 | * SUCH DAMAGE.
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28 | */
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29 | |||
30 | #ifndef _ARM_CPU_H
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31 | #define _ARM_CPU_H
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32 | |||
33 | /*
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34 | * Processor Status Register
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35 | */
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36 | #define PSR_MODE 0x0000001f |
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37 | #define PSR_USR_MODE 0x00000010 |
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38 | #define PSR_FIQ_MODE 0x00000011 |
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39 | #define PSR_IRQ_MODE 0x00000012 |
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40 | #define PSR_SVC_MODE 0x00000013 |
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41 | #define PSR_ABT_MODE 0x00000017 |
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42 | #define PSR_UND_MODE 0x0000001b |
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43 | #define PSR_SYS_MODE 0x0000001f |
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44 | |||
45 | #define PSR_THUMB 0x00000020 |
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46 | |||
47 | #define PSR_INT_MASK 0x000000c0 |
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48 | #define PSR_FIQ_DIS 0x00000040 |
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49 | #define PSR_IRQ_DIS 0x00000080 |
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50 | |||
51 | #ifdef __gba__
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52 | #define PSR_APP_MODE PSR_SYS_MODE
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53 | #else
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54 | #define PSR_APP_MODE PSR_USR_MODE
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55 | #endif
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56 | |||
57 | /*
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58 | * Contorl register CP15 register 1
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59 | */
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60 | #define CTL_MMU 0x000000001 /* M: MMU/Protection unit enable */ |
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61 | #define CTL_AFLT 0x000000002 /* A: Alignment fault enable */ |
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62 | #define CTL_CACHE 0x000000004 /* C: Cache enable */ |
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63 | #define CTL_WBUF 0x000000008 /* W: Write buffer enable */ |
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64 | #define CTL_32BP 0x000000010 /* P: 32-bit exception handlers */ |
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65 | #define CTL_32BD 0x000000020 /* D: 32-bit addressing */ |
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66 | #define CTL_LABT 0x000000040 /* L: Late abort enable */ |
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67 | #define CTL_BIGEND 0x000000080 /* B: Big-endian mode */ |
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68 | #define CTL_SYSP 0x000000100 /* S: System protection bit */ |
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69 | #define CTL_ROMP 0x000000200 /* R: ROM protection bit */ |
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70 | #define CTL_BPRD 0x000000800 /* Z: Branch prediction enable */ |
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71 | #define CTL_ICACHE 0x000001000 /* I: Instruction cache enable */ |
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72 | #define CTL_HIVEC 0x000002000 /* V: Vector relocation */ |
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73 | |||
74 | #define CTL_DEFAULT (CTL_32BP | CTL_32BD | CTL_LABT)
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75 | |||
76 | #ifndef __ASSEMBLY__
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77 | |||
78 | __BEGIN_DECLS |
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79 | void cpu_init(void); |
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80 | __END_DECLS |
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81 | |||
82 | #endif /* !__ASSEMBLY__ */ |
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83 | #endif /* !_ARM_CPU_H */ |