root / prex-0.9.0 / bsp / hal / arm / arch / locore.S @ 03e9c04a
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1 | 03e9c04a | Brad Neuman | /*- |
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2 | * Copyright (c) 2005-2007, Kohsuke Ohtani |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * 1. Redistributions of source code must retain the above copyright |
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9 | * notice, this list of conditions and the following disclaimer. |
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10 | * 2. Redistributions in binary form must reproduce the above copyright |
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11 | * notice, this list of conditions and the following disclaimer in the |
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12 | * documentation and/or other materials provided with the distribution. |
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13 | * 3. Neither the name of the author nor the names of any co-contributors |
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14 | * may be used to endorse or promote products derived from this software |
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15 | * without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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27 | * SUCH DAMAGE. |
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28 | */ |
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29 | |||
30 | /* |
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31 | * locore.S - low level platform support |
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32 | */ |
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33 | |||
34 | #include <conf/config.h> |
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35 | #include <machine/asm.h> |
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36 | #include <machine/syspage.h> |
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37 | #include <machine/memory.h> |
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38 | #include <sys/errno.h> |
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39 | #include <context.h> |
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40 | #include <trap.h> |
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41 | #include <cpu.h> |
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42 | |||
43 | .section ".text","ax" |
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44 | .code 32 |
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45 | |||
46 | /* |
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47 | * Kernel start point |
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48 | */ |
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49 | ENTRY(kernel_start) |
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50 | #ifdef CONFIG_MMU |
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51 | b reset_entry /* Relative jump */ |
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52 | #endif |
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53 | vector_start: |
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54 | /* |
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55 | * Exception vector |
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56 | * |
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57 | * This table will be copied to an appropriate location. |
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58 | * (the location is platform specific.) |
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59 | */ |
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60 | ldr pc, reset_target /* 0x00 mode: svc */ |
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61 | ldr pc, undefined_target /* 0x04 mode: ? */ |
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62 | ldr pc, swi_target /* 0x08 mode: svc */ |
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63 | ldr pc, prefetch_target /* 0x0c mode: abort */ |
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64 | ldr pc, abort_target /* 0x10 mode: abort */ |
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65 | nop /* 0x14 reserved */ |
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66 | ldr pc, irq_target /* 0x18 mode: irq */ |
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67 | ldr pc, fiq_target /* 0x1c mode: fiq */ |
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68 | |||
69 | reset_target: .word reset_entry |
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70 | undefined_target: .word undefined_entry |
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71 | swi_target: .word syscall_entry |
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72 | prefetch_target: .word prefetch_entry |
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73 | abort_target: .word abort_entry |
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74 | irq_target: .word interrupt_entry |
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75 | fiq_target: .word fiq_entry |
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76 | |||
77 | vector_end: |
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78 | |||
79 | .global bootinfo |
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80 | bootinfo: .word BOOTINFO |
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81 | boot_stack: .word BOOTSTKTOP |
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82 | int_stack: .word INTSTKTOP - 0x100 |
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83 | irq_mode_stack: .word INTSTKTOP |
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84 | sys_mode_stack: .word SYSSTKTOP |
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85 | abort_mode_stack: .word ABTSTKTOP |
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86 | irq_nesting: .word irq_nesting_value |
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87 | curspl: .word curspl_value |
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88 | init_done: .word init_done_value |
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89 | #ifdef CONFIG_MMU |
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90 | reload_pc_target: .word reload_pc |
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91 | #endif |
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92 | |||
93 | ENTRY(reset_entry) |
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94 | /* |
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95 | * Setup stack pointer for each processor mode |
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96 | */ |
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97 | mov r0, #(PSR_IRQ_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS) |
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98 | msr cpsr, r0 |
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99 | ldr sp, irq_mode_stack /* Set IRQ mode stack */ |
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100 | |||
101 | mov r0, #(PSR_UND_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS) |
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102 | msr cpsr, r0 |
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103 | ldr sp, abort_mode_stack /* Set Undefined mode stack */ |
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104 | |||
105 | mov r0, #(PSR_ABT_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS) |
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106 | msr cpsr, r0 |
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107 | ldr sp, abort_mode_stack /* Set Abort mode stack */ |
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108 | |||
109 | mov r0, #(PSR_SYS_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS) |
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110 | msr cpsr, r0 |
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111 | ldr sp, sys_mode_stack /* Set SYS mode stack */ |
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112 | |||
113 | mov r0, #(PSR_SVC_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS) |
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114 | msr cpsr, r0 |
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115 | ldr sp, boot_stack /* Set SVC mode stack */ |
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116 | |||
117 | /* It's svc mode now. */ |
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118 | |||
119 | #ifdef CONFIG_MMU |
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120 | /* |
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121 | * Setup control register |
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122 | */ |
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123 | mov r0, #CTL_DEFAULT |
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124 | mcr p15, 0, r0, c1, c0, 0 |
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125 | |||
126 | /* |
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127 | * Initialize page table |
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128 | * The physical address 0-4M is mapped on virtual address 2G. |
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129 | */ |
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130 | mov r1, #BOOT_PGD_PHYS /* Clear page directory */ |
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131 | mov r2, #(BOOT_PGD_PHYS + 0x4000) /* +16k */ |
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132 | mov r0, #0 |
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133 | 1: |
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134 | str r0, [r1], #4 |
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135 | teq r1, r2 |
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136 | bne 1b |
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137 | |||
138 | mov r1, #(BOOT_PGD_PHYS + 0x2000) /* Set PTE0 address in pgd */ |
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139 | mov r0, #BOOT_PTE0_PHYS /* WBUF/CACHE/SYSTEM attribute */ |
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140 | orr r0, r0, #0x03 |
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141 | str r0, [r1] |
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142 | |||
143 | mov r1, #BOOT_PTE0_PHYS /* Fill boot page table entry */ |
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144 | add r2, r1, #0x1000 |
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145 | mov r0, #0x1e |
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146 | 1: |
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147 | str r0, [r1], #4 |
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148 | add r0, r0, #0x1000 |
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149 | teq r1, r2 |
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150 | bne 1b |
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151 | |||
152 | /* |
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153 | * Enable paging |
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154 | * The physical address 0-4M is temporarily mapped to virtial |
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155 | * address 0-4M. This is needed to enable paging. |
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156 | */ |
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157 | mov r1, #BOOT_PGD_PHYS /* Set PTE0 address in pgd */ |
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158 | mov r0, #BOOT_PTE0_PHYS /* WBUF/CACHE/SYSTEM attribute */ |
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159 | orr r0, r0, #0x03 |
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160 | str r0, [r1] |
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161 | |||
162 | mov r0, #0 |
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163 | mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ |
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164 | mcr p15, 0, r0, c8, c7, 0 /* flush I,D TLBs */ |
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165 | mov r1, #BOOT_PGD_PHYS |
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166 | mcr p15, 0, r1, c2, c0, 0 /* load page table pointer */ |
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167 | mov r0, #-1 |
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168 | mcr p15, 0, r0, c3, c0 /* load domain access register */ |
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169 | mrc p15, 0, r0, c1, c0, 0 |
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170 | orr r0, r0, #0x1000 /* I-cache enable */ |
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171 | orr r0, r0, #0x003d /* Write buffer, mmu */ |
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172 | mcr p15, 0, r0, c1, c0, 0 |
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173 | |||
174 | /* |
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175 | * Reload PC register for virutal address. |
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176 | */ |
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177 | ldr pc, reload_pc_target /* Reset pc here */ |
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178 | reload_pc: |
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179 | |||
180 | /* |
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181 | * Unmap 0-4M. |
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182 | * Since the first page must be accessible for exception |
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183 | * vector, we have to map it later. |
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184 | */ |
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185 | mov r1, #BOOT_PGD_PHYS /* Set PTE0 address in pgd */ |
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186 | add r1, r1, #KERNBASE |
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187 | mov r0, #0 |
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188 | str r0, [r1] |
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189 | mcr p15, 0, r0, c8, c7, 0 /* flush I,D TLBs */ |
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190 | |||
191 | #endif /* !CONFIG_MMU */ |
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192 | |||
193 | /* |
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194 | * Clear kernel BSS |
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195 | */ |
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196 | ldr r1, =__bss |
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197 | ldr r2, =__end |
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198 | mov r0, #0 |
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199 | cmp r1, r2 |
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200 | beq 2f |
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201 | 1: |
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202 | str r0, [r1], #4 |
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203 | cmp r1, r2 |
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204 | bls 1b |
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205 | 2: |
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206 | |||
207 | /* |
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208 | * Initilize spl. |
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209 | */ |
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210 | ldr r1, curspl /* curspl = 15 */ |
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211 | mov r2, #15 |
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212 | str r2, [r1] |
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213 | |||
214 | /* |
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215 | * Jump to kernel main routine |
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216 | */ |
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217 | b main |
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218 | |||
219 | /* |
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220 | * Relocate exception vector |
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221 | * |
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222 | * void vector_copy(vaddr_t dest); |
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223 | */ |
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224 | ENTRY(vector_copy) |
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225 | ldr r1, =vector_start |
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226 | ldr r2, =vector_end |
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227 | 1: |
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228 | ldmia r1!, {r3} |
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229 | stmia r0!, {r3} |
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230 | teq r1, r2 |
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231 | bne 1b |
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232 | mov pc, lr |
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233 | |||
234 | #ifdef CONFIG_CACHE |
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235 | /* |
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236 | * Enable cache |
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237 | */ |
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238 | ENTRY(cache_init) |
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239 | mov pc, lr |
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240 | #endif |
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241 | |||
242 | /* |
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243 | * Interrupt entry point |
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244 | */ |
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245 | /* |
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246 | * Memo: GBA BIOS interrupt handler. |
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247 | * |
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248 | * stmfd sp!, {r0-r3,r12,lr} |
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249 | * mov r0, #0x4000000 |
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250 | * adr lr, IntRet |
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251 | * ldr pc, [r0,#-4] @ pc = [0x3007ffc] |
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252 | *IntRet: |
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253 | * ldmfd sp!, {r0-r3,r12,lr} |
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254 | * subs pc, lr, #4 |
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255 | */ |
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256 | ENTRY(interrupt_entry) |
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257 | #ifdef __gba__ |
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258 | ldmfd sp!, {r0-r3,r12,lr} /* Discard GBA BIOS's stack */ |
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259 | #endif |
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260 | stmfd sp, {r0-r4} /* Save work registers */ |
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261 | sub r4, sp, #(4*5) /* r4: Pointer to saved registers */ |
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262 | mrs r0, spsr /* r0: cpsr */ |
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263 | sub r3, lr, #4 /* r3: original pc */ |
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264 | |||
265 | mrs r1, cpsr /* Set processor to SVC mode */ |
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266 | bic r1, r1, #PSR_MODE |
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267 | orr r1, r1, #PSR_SVC_MODE |
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268 | msr cpsr_c, r1 |
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269 | |||
270 | mov r1, sp /* r1: svc_sp */ |
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271 | mov r2, lr /* r2: svc_lr */ |
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272 | stmfd sp!, {r0-r3} /* Push cpsr, svc_sp, svc_lr, pc */ |
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273 | ldmfd r4, {r0-r4} /* Restore work registers */ |
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274 | sub sp, sp, #(4*15) |
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275 | stmia sp, {r0-r14}^ /* Push r0-r14 */ |
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276 | nop /* Instruction gap for stm^ */ |
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277 | |||
278 | ldr r4, irq_nesting /* Increment IRQ nesting level */ |
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279 | ldr r5, [r4] /* r5: Previous nesting level */ |
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280 | add r0, r5, #1 |
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281 | str r0, [r4] |
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282 | |||
283 | mov r7, sp /* Save stack */ |
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284 | ldr r3, int_stack /* Adjust stack for IRQ */ |
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285 | cmp r5, #0 /* Outermost interrupt? */ |
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286 | moveq sp, r3 /* If outermost, switch stack */ |
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287 | bleq sched_lock /* If outermost, lock scheduler */ |
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288 | bl interrupt_handler /* Call main interrupt handler */ |
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289 | |||
290 | mov sp, r7 /* Restore stack */ |
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291 | str r5, [r4] /* Restore IRQ nesting level */ |
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292 | cmp r5, #0 /* Outermost interrupt? */ |
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293 | bne interrupt_ret |
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294 | bl sched_unlock /* Try to preempt */ |
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295 | |||
296 | ldr r0, [sp, #REG_CPSR] /* Get previous mode */ |
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297 | and r0, r0, #PSR_MODE |
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298 | cmp r0, #PSR_APP_MODE /* Return to application mode? */ |
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299 | bne interrupt_ret |
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300 | |||
301 | mrs r5, cpsr /* Enable IRQ */ |
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302 | bic r4, r5, #0xc0 |
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303 | msr cpsr_c, r4 |
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304 | bl exception_deliver /* Check exception */ |
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305 | msr cpsr_c, r5 /* Restore IRQ */ |
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306 | interrupt_ret: |
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307 | mov r0, sp |
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308 | ldr r1, [r0, #REG_CPSR] /* Restore spsr */ |
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309 | msr spsr_all, r1 |
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310 | ldmfd r0, {r0-r14}^ /* Restore user mode registers */ |
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311 | nop /* Instruction gap for ldm^ */ |
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312 | add sp, sp, #(4*16) |
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313 | ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ |
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314 | |||
315 | /* |
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316 | * System call entry |
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317 | */ |
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318 | .global syscall_ret |
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319 | ENTRY(syscall_entry) |
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320 | #ifdef __gba__ |
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321 | mov r5, lr /* Syscall stub already saved r5 */ |
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322 | mrs r12, cpsr /* Set processor to SVC mode */ |
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323 | bic r12, r12, #PSR_MODE |
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324 | orr r12, r12, #PSR_SVC_MODE |
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325 | msr cpsr_c, r12 |
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326 | mov lr, r5 |
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327 | #endif |
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328 | sub sp, sp, #CTXREGS /* Adjust stack */ |
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329 | stmia sp, {r0-r14}^ /* Push r0-r14 */ |
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330 | nop /* Instruction gap for stm^ */ |
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331 | mrs r5, spsr /* Push cpsr */ |
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332 | str r5, [sp, #REG_CPSR] |
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333 | add r5, sp, #CTXREGS |
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334 | str r5, [sp, #REG_SVCSP] /* Push svc_sp */ |
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335 | str lr, [sp, #REG_SVCLR] /* Push svc_lr */ |
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336 | str lr, [sp, #REG_PC] /* Push pc */ |
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337 | #ifndef __gba__ |
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338 | ldr r4, [lr, #-4] /* Get SWI number */ |
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339 | bic r4, r4, #0xff000000 |
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340 | |||
341 | mrs r5, cpsr /* Enable IRQ */ |
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342 | bic r5, r5, #0xc0 |
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343 | msr cpsr_c, r5 |
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344 | #endif |
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345 | |||
346 | stmfd sp!, {r4} |
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347 | bl syscall_handler /* System call dispatcher */ |
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348 | ldmfd sp!, {r4} |
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349 | |||
350 | cmp r4, #0 /* Skip storing error if exception_return */ |
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351 | strne r0, [sp] /* Set return value to r0 */ |
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352 | bl exception_deliver /* Check exception */ |
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353 | syscall_ret: |
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354 | mrs r5, cpsr /* Disable IRQ */ |
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355 | orr r5, r5, #0xc0 |
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356 | msr cpsr_c, r5 |
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357 | mov r5, sp |
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358 | ldr r1, [r5, #REG_CPSR] /* Restore spsr */ |
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359 | msr spsr_all, r1 |
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360 | ldmfd r5, {r0-r14}^ /* Restore user mode registers */ |
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361 | nop /* Instruction gap for ldm^ */ |
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362 | add sp, sp, #REG_SVCSP |
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363 | ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ |
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364 | |||
365 | /* |
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366 | * Undefined instruction |
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367 | */ |
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368 | ENTRY(undefined_entry) |
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369 | sub sp, sp, #CTXREGS /* Adjust stack */ |
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370 | stmia sp, {r0-r14}^ /* Push r0-r14 */ |
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371 | nop /* Instruction gap for stm^ */ |
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372 | mov r0, #TRAP_UNDEFINED |
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373 | b trap_common |
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374 | |||
375 | /* |
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376 | * Prefetch abort |
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377 | */ |
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378 | ENTRY(prefetch_entry) |
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379 | sub lr, lr, #8 /* Adjust the lr */ |
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380 | sub sp, sp, #CTXREGS /* Adjust stack */ |
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381 | stmia sp, {r0-r14}^ /* Push r0-r14 */ |
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382 | nop /* Instruction gap for stm^ */ |
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383 | mov r0, #TRAP_PREFETCH_ABORT |
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384 | b trap_common |
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385 | |||
386 | /* |
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387 | * Data abort |
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388 | */ |
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389 | ENTRY(abort_entry) |
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390 | sub lr, lr, #4 /* Adjust the lr */ |
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391 | sub sp, sp, #CTXREGS /* Adjust stack */ |
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392 | stmia sp, {r0-r14}^ /* Push r0-r14 */ |
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393 | nop /* Instruction gap for stm^ */ |
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394 | mov r0, #TRAP_DATA_ABORT |
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395 | b trap_common |
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396 | |||
397 | /* |
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398 | * Common entry for all traps |
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399 | * r0 - trap type |
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400 | */ |
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401 | ENTRY(trap_common) |
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402 | add r5, sp, #CTXREGS |
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403 | str r5, [sp, #REG_SVCSP] /* Push svc_sp */ |
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404 | str lr, [sp, #REG_PC] /* Push pc */ |
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405 | mrs r5, spsr /* Push cpsr */ |
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406 | str r5, [sp, #REG_CPSR] |
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407 | |||
408 | str r0, [sp, #REG_R0] /* Set trap type to R0 */ |
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409 | mov r0, sp |
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410 | bl trap_handler |
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411 | |||
412 | mov r5, sp |
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413 | ldr r1, [r5, #REG_CPSR] /* Restore cpsr */ |
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414 | msr spsr_all, r1 |
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415 | ldr lr, [r5, #REG_PC] /* Restore pc (lr) */ |
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416 | ldr sp, [r5, #REG_SVCSP] /* Restore svc_sp */ |
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417 | ldmfd r5, {r0-r14}^ /* Restore user mode registers */ |
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418 | nop /* Instruction gap for ldm^ */ |
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419 | movs pc, lr /* Exit, with restoring cpsr */ |
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420 | |||
421 | ENTRY(fiq_entry) |
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422 | b fiq_entry /* Not support... */ |
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423 | |||
424 | /* |
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425 | * Switch register context. |
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426 | * r0 = previous kern_regs, r1 = next kern_regs |
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427 | * Interrupts must be disabled by caller. |
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428 | * |
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429 | * syntax - void cpu_switch(kern_regs *prev, kern_regs *next) |
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430 | * |
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431 | * Note: GCC uses r0-r3,r12 as scratch registers |
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432 | */ |
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433 | ENTRY(cpu_switch) |
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434 | stmia r0, {r4-r11, sp, lr} /* Save previous register context */ |
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435 | ldmia r1, {r4-r11, sp, pc} /* Restore next register context */ |
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436 | |||
437 | /* |
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438 | * Entry point for kernel thread |
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439 | */ |
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440 | ENTRY(kernel_thread_entry) |
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441 | mov r0, r5 /* Set argument */ |
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442 | mov pc, r4 /* Jump to kernel thread */ |
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443 | 1: |
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444 | b 1b |
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445 | |||
446 | |||
447 | /* |
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448 | * Copy data from user to kernel space. |
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449 | * Returns 0 on success, or EFAULT on page fault. |
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450 | * |
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451 | * syntax - int copyin(const void *uaddr, void *kaddr, size_t len) |
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452 | */ |
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453 | .global known_fault1 |
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454 | ENTRY(copyin) |
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455 | mov r12, sp |
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456 | stmdb sp!, {r4, r11, r12, lr, pc} |
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457 | sub r11, r12, #4 |
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458 | cmp r0, #(USERLIMIT) |
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459 | bhi copy_fault |
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460 | mov r12, #0 |
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461 | b 2f |
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462 | 1: |
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463 | ldrb r3, [r12, r0] |
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464 | known_fault1: /* May be fault here */ |
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465 | strb r3, [r12, r1] |
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466 | add r12, r12, #1 |
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467 | 2: |
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468 | subs r2, r2, #1 |
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469 | bcs 1b |
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470 | mov r0, #0 /* Set no error */ |
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471 | ldmia sp, {r4, r11, sp, pc} |
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472 | |||
473 | /* |
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474 | * Copy data to user from kernel space. |
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475 | * Returns 0 on success, or EFAULT on page fault. |
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476 | * |
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477 | * syntax - int copyout(const void *kaddr, void *uaddr, size_t len) |
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478 | */ |
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479 | .global known_fault2 |
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480 | ENTRY(copyout) |
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481 | mov r12, sp |
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482 | stmdb sp!, {r4, r11, r12, lr, pc} |
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483 | sub r11, r12, #4 |
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484 | cmp r1, #(USERLIMIT) |
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485 | bhi copy_fault |
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486 | mov r12, #0 |
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487 | b 2f |
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488 | 1: |
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489 | ldrb r3, [r12, r0] |
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490 | known_fault2: /* May be fault here */ |
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491 | strb r3, [r12, r1] |
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492 | add r12, r12, #1 |
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493 | 2: |
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494 | subs r2, r2, #1 |
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495 | bcs 1b |
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496 | mov r0, #0 /* Set no error */ |
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497 | ldmia sp, {r4, r11, sp, pc} |
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498 | |||
499 | /* |
||
500 | * copyinstr - Copy string from user space. |
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501 | * Returns 0 on success, or EFAULT on page fault, or ENAMETOOLONG. |
||
502 | * |
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503 | * syntax - int copyinstr(const char *uaddr, void *kaddr, size_t len); |
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504 | */ |
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505 | .global known_fault3 |
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506 | ENTRY(copyinstr) |
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507 | mov r12, sp |
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508 | stmdb sp!, {r4, r11, r12, lr, pc} |
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509 | sub r11, r12, #4 |
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510 | cmp r0, #(USERLIMIT) |
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511 | bhi copy_fault |
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512 | mov r12, #0 |
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513 | b 2f |
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514 | 1: |
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515 | ldrb r3, [r12, r0] |
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516 | known_fault3: /* May be fault here */ |
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517 | strb r3, [r12, r1] |
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518 | cmp r3, #0 |
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519 | beq 3f |
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520 | add r12, r12, #1 |
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521 | 2: |
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522 | subs r2, r2, #1 |
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523 | bcs 1b |
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524 | mov r0, #(ENAMETOOLONG) |
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525 | b 4f |
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526 | 3: |
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527 | mov r0, #0 /* Set no error */ |
||
528 | 4: |
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529 | ldmia sp, {r4, r11, sp, pc} |
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530 | |||
531 | /* |
||
532 | * Fault entry for user access |
||
533 | */ |
||
534 | ENTRY(copy_fault) |
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535 | mov r0, #(EFAULT) |
||
536 | ldmia sp, {r4, r11, sp, pc} |
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537 | |||
538 | |||
539 | /* |
||
540 | * int spl0(void); |
||
541 | */ |
||
542 | ENTRY(spl0) |
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543 | ldr r1, curspl /* curspl = 0 */ |
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544 | ldr r0, [r1] |
||
545 | mov r2, #0 |
||
546 | str r2, [r1] |
||
547 | |||
548 | mrs r1, cpsr /* Enable interrupt */ |
||
549 | bic r1, r1, #0xc0 |
||
550 | msr cpsr_c, r1 |
||
551 | mov pc, lr |
||
552 | |||
553 | /* |
||
554 | * int splhigh(void); |
||
555 | */ |
||
556 | ENTRY(splhigh) |
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557 | mrs r1, cpsr /* Disable interrupt */ |
||
558 | orr r1, r1, #0xc0 |
||
559 | msr cpsr_c, r1 |
||
560 | |||
561 | ldr r1, curspl /* curspl = 15 */ |
||
562 | ldr r0, [r1] |
||
563 | mov r2, #15 |
||
564 | str r2, [r1] |
||
565 | mov pc, lr |
||
566 | |||
567 | /* |
||
568 | * void splx(int s); |
||
569 | */ |
||
570 | ENTRY(splx) |
||
571 | mov r3, r0 /* r3: new spl */ |
||
572 | ldr r1, curspl |
||
573 | ldr r0, [r1] |
||
574 | cmp r3, r0 |
||
575 | moveq pc, lr /* Return if equal */ |
||
576 | str r3, [r1] |
||
577 | |||
578 | cmp r3, #0 |
||
579 | mrs r1, cpsr |
||
580 | bic r1, r1, #0xc0 |
||
581 | orrne r1, r1, #0xc0 /* Disable interrupt if curspl != 0 */ |
||
582 | msr cpsr_c, r1 |
||
583 | mov pc, lr |
||
584 | |||
585 | |||
586 | /* |
||
587 | * void sploff(void); |
||
588 | */ |
||
589 | ENTRY(sploff) |
||
590 | mrs r0, cpsr |
||
591 | orr r0, r0, #0xc0 |
||
592 | msr cpsr_c, r0 |
||
593 | mov pc, lr |
||
594 | |||
595 | /* |
||
596 | * void splon(void); |
||
597 | */ |
||
598 | ENTRY(splon) |
||
599 | mrs r0, cpsr |
||
600 | bic r0, r0, #0xc0 |
||
601 | msr cpsr_c, r0 |
||
602 | mov pc, lr |
||
603 | |||
604 | /* |
||
605 | * Interrupt nest counter. |
||
606 | * |
||
607 | * This counter is incremented in the entry of interrupt handler |
||
608 | * to switch the interrupt stack. Since all interrupt handlers |
||
609 | * share same one interrupt stack, each handler must pay attention |
||
610 | * to the stack overflow. |
||
611 | */ |
||
612 | .section ".bss" |
||
613 | irq_nesting_value: |
||
614 | .long 0 |
||
615 | |||
616 | /* |
||
617 | * Current spl |
||
618 | */ |
||
619 | curspl_value: |
||
620 | .long 0 |
||
621 | |||
622 | /* |
||
623 | * Init flag for debug |
||
624 | */ |
||
625 | init_done_value: |
||
626 | .long 0 |
||
627 | |||
628 | .end |