root / prex-0.9.0 / bsp / drv / dev / serial / pl011.c @ 03e9c04a
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1 | 03e9c04a | Brad Neuman | /*-
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2 | * Copyright (c) 2008-2009, Kohsuke Ohtani
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3 | * All rights reserved.
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4 | *
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5 | * Redistribution and use in source and binary forms, with or without
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6 | * modification, are permitted provided that the following conditions
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7 | * are met:
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8 | * 1. Redistributions of source code must retain the above copyright
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9 | * notice, this list of conditions and the following disclaimer.
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10 | * 2. Redistributions in binary form must reproduce the above copyright
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11 | * notice, this list of conditions and the following disclaimer in the
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12 | * documentation and/or other materials provided with the distribution.
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13 | * 3. Neither the name of the author nor the names of any co-contributors
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14 | * may be used to endorse or promote products derived from this software
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15 | * without specific prior written permission.
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16 | *
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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27 | * SUCH DAMAGE.
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28 | */
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29 | |||
30 | /*
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31 | * pl011.c - ARM PrimeCell PL011 UART
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32 | */
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33 | |||
34 | #include <driver.h> |
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35 | #include <tty.h> |
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36 | #include <serial.h> |
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37 | |||
38 | /* #define DEBUG_PL011 1 */
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39 | |||
40 | #ifdef DEBUG_PL011
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41 | #define DPRINTF(a) printf a
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42 | #else
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43 | #define DPRINTF(a)
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44 | #endif
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45 | |||
46 | #define UART_BASE CONFIG_PL011_BASE
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47 | #define UART_IRQ CONFIG_PL011_IRQ
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48 | #define UART_CLK 14745600 |
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49 | #define BAUD_RATE 115200 |
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50 | |||
51 | /* UART Registers */
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52 | #define UART_DR (UART_BASE + 0x00) |
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53 | #define UART_RSR (UART_BASE + 0x04) |
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54 | #define UART_ECR (UART_BASE + 0x04) |
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55 | #define UART_FR (UART_BASE + 0x18) |
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56 | #define UART_IBRD (UART_BASE + 0x24) |
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57 | #define UART_FBRD (UART_BASE + 0x28) |
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58 | #define UART_LCRH (UART_BASE + 0x2c) |
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59 | #define UART_CR (UART_BASE + 0x30) |
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60 | #define UART_IMSC (UART_BASE + 0x38) |
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61 | #define UART_MIS (UART_BASE + 0x40) |
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62 | #define UART_ICR (UART_BASE + 0x44) |
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63 | |||
64 | /* Flag register */
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65 | #define FR_RXFE 0x10 /* Receive FIFO empty */ |
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66 | #define FR_TXFF 0x20 /* Transmit FIFO full */ |
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67 | |||
68 | /* Masked interrupt status register */
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69 | #define MIS_RX 0x10 /* Receive interrupt */ |
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70 | #define MIS_TX 0x20 /* Transmit interrupt */ |
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71 | |||
72 | /* Interrupt clear register */
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73 | #define ICR_RX 0x10 /* Clear receive interrupt */ |
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74 | #define ICR_TX 0x20 /* Clear transmit interrupt */ |
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75 | |||
76 | /* Line control register (High) */
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77 | #define LCRH_WLEN8 0x60 /* 8 bits */ |
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78 | #define LCRH_FEN 0x10 /* Enable FIFO */ |
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79 | |||
80 | /* Control register */
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81 | #define CR_UARTEN 0x0001 /* UART enable */ |
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82 | #define CR_TXE 0x0100 /* Transmit enable */ |
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83 | #define CR_RXE 0x0200 /* Receive enable */ |
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84 | |||
85 | /* Interrupt mask set/clear register */
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86 | #define IMSC_RX 0x10 /* Receive interrupt mask */ |
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87 | #define IMSC_TX 0x20 /* Transmit interrupt mask */ |
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88 | |||
89 | /* Forward functions */
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90 | static int pl011_init(struct driver *); |
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91 | static void pl011_xmt_char(struct serial_port *, char); |
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92 | static char pl011_rcv_char(struct serial_port *); |
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93 | static void pl011_set_poll(struct serial_port *, int); |
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94 | static void pl011_start(struct serial_port *); |
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95 | static void pl011_stop(struct serial_port *); |
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96 | |||
97 | |||
98 | struct driver pl011_driver = {
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99 | /* name */ "pl011", |
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100 | /* devops */ NULL, |
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101 | /* devsz */ 0, |
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102 | /* flags */ 0, |
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103 | /* probe */ NULL, |
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104 | /* init */ pl011_init,
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105 | /* detach */ NULL, |
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106 | }; |
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107 | |||
108 | static struct serial_ops pl011_ops = { |
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109 | /* xmt_char */ pl011_xmt_char,
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110 | /* rcv_char */ pl011_rcv_char,
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111 | /* set_poll */ pl011_set_poll,
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112 | /* start */ pl011_start,
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113 | /* stop */ pl011_stop,
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114 | }; |
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115 | |||
116 | static struct serial_port pl011_port; |
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117 | |||
118 | |||
119 | static void |
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120 | pl011_xmt_char(struct serial_port *sp, char c) |
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121 | { |
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122 | |||
123 | while (bus_read_32(UART_FR) & FR_TXFF)
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124 | ; |
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125 | bus_write_32(UART_DR, (uint32_t)c); |
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126 | } |
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127 | |||
128 | static char |
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129 | pl011_rcv_char(struct serial_port *sp)
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130 | { |
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131 | char c;
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132 | |||
133 | while (bus_read_32(UART_FR) & FR_RXFE)
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134 | ; |
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135 | c = bus_read_32(UART_DR) & 0xff;
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136 | return c;
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137 | } |
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138 | |||
139 | static void |
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140 | pl011_set_poll(struct serial_port *sp, int on) |
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141 | { |
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142 | |||
143 | if (on) {
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144 | /*
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145 | * Disable interrupt for polling mode.
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146 | */
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147 | bus_write_32(UART_IMSC, 0);
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148 | } else
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149 | bus_write_32(UART_IMSC, (IMSC_RX | IMSC_TX)); |
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150 | } |
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151 | |||
152 | static int |
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153 | pl011_isr(void *arg)
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154 | { |
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155 | struct serial_port *sp = arg;
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156 | int c;
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157 | uint32_t mis; |
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158 | |||
159 | mis = bus_read_32(UART_MIS); |
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160 | |||
161 | if (mis & MIS_RX) {
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162 | /*
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163 | * Receive interrupt
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164 | */
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165 | while (bus_read_32(UART_FR) & FR_RXFE)
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166 | ; |
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167 | do {
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168 | c = bus_read_32(UART_DR); |
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169 | serial_rcv_char(sp, c); |
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170 | } while ((bus_read_32(UART_FR) & FR_RXFE) == 0); |
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171 | |||
172 | /* Clear interrupt status */
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173 | bus_write_32(UART_ICR, ICR_RX); |
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174 | } |
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175 | if (mis & MIS_TX) {
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176 | /*
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177 | * Transmit interrupt
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178 | */
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179 | serial_xmt_done(sp); |
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180 | |||
181 | /* Clear interrupt status */
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182 | bus_write_32(UART_ICR, ICR_TX); |
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183 | } |
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184 | return 0; |
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185 | } |
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186 | |||
187 | static void |
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188 | pl011_start(struct serial_port *sp)
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189 | { |
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190 | uint32_t divider, remainder, fraction; |
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191 | |||
192 | bus_write_32(UART_CR, 0); /* Disable everything */ |
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193 | bus_write_32(UART_ICR, 0x07ff); /* Clear all interrupt status */ |
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194 | |||
195 | /*
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196 | * Set baud rate:
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197 | * IBRD = UART_CLK / (16 * BAUD_RATE)
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198 | * FBRD = ROUND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
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199 | */
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200 | divider = UART_CLK / (16 * BAUD_RATE);
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201 | remainder = UART_CLK % (16 * BAUD_RATE);
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202 | fraction = (8 * remainder / BAUD_RATE) >> 1; |
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203 | fraction += (8 * remainder / BAUD_RATE) & 1; |
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204 | bus_write_32(UART_IBRD, divider); |
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205 | bus_write_32(UART_FBRD, fraction); |
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206 | |||
207 | /* Set N, 8, 1, FIFO enable */
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208 | bus_write_32(UART_LCRH, (LCRH_WLEN8 | LCRH_FEN)); |
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209 | |||
210 | /* Enable UART */
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211 | bus_write_32(UART_CR, (CR_RXE | CR_TXE | CR_UARTEN)); |
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212 | |||
213 | /* Install interrupt handler */
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214 | sp->irq = irq_attach(UART_IRQ, IPL_COMM, 0, pl011_isr, IST_NONE, sp);
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215 | |||
216 | /* Enable TX/RX interrupt */
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217 | bus_write_32(UART_IMSC, (IMSC_RX | IMSC_TX)); |
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218 | } |
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219 | |||
220 | static void |
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221 | pl011_stop(struct serial_port *sp)
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222 | { |
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223 | |||
224 | bus_write_32(UART_IMSC, 0); /* Disable all interrupts */ |
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225 | bus_write_32(UART_CR, 0); /* Disable everything */ |
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226 | } |
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227 | |||
228 | static int |
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229 | pl011_init(struct driver *self)
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230 | { |
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231 | |||
232 | serial_attach(&pl011_ops, &pl011_port); |
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233 | return 0; |
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234 | } |