root / prex-0.9.0 / bsp / drv / dev / dma / i8237.c @ 03e9c04a
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1 | 03e9c04a | Brad Neuman | /*-
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2 | * Copyright (c) 2005, Kohsuke Ohtani
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3 | * All rights reserved.
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4 | *
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5 | * Redistribution and use in source and binary forms, with or without
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6 | * modification, are permitted provided that the following conditions
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7 | * are met:
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8 | * 1. Redistributions of source code must retain the above copyright
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9 | * notice, this list of conditions and the following disclaimer.
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10 | * 2. Redistributions in binary form must reproduce the above copyright
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11 | * notice, this list of conditions and the following disclaimer in the
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12 | * documentation and/or other materials provided with the distribution.
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13 | * 3. Neither the name of the author nor the names of any co-contributors
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14 | * may be used to endorse or promote products derived from this software
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15 | * without specific prior written permission.
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16 | *
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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27 | * SUCH DAMAGE.
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28 | */
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29 | |||
30 | /*
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31 | * i8237.c - Intel 8237 DMA controller
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32 | */
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33 | |||
34 | /**
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35 | * Memo:
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36 | *
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37 | * [Mode Register]
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38 | *
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39 | * Bits Function
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40 | * -------- Mode Selection
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41 | * 00 Demand Mode
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42 | * 01 Single Mode
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43 | * 10 Block Mode
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44 | * 11 Cascade Mode
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45 | * -------- Address Increment/Decrement
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46 | * 1 Address Decrement
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47 | * 0 Address Increment
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48 | * -------- Auto-Initialization Enable
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49 | * 1 Auto-Initialization DMA
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50 | * 0 Single-Cycle DMA
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51 | * -------- Transfer Type
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52 | * 00 Verify
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53 | * 01 Write
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54 | * 10 Read
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55 | * 11 Illegal
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56 | * -------- Channel Selection
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57 | * 00 Channel 0 (4)
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58 | * 01 Channel 1 (5)
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59 | * 10 Channel 2 (6)
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60 | * 11 Channel 3 (7)
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61 | *
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62 | * [Single Mask Register]
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63 | *
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64 | * Bits Function
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65 | * --------
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66 | * 00000 Unused, Set to 0
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67 | * -------- Set/Clear Mask
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68 | * 1 Set (Disable Channel)
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69 | * 0 Clear (Enable Channel)
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70 | * -------- Channel Selection
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71 | * 00 Channel 0 (4)
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72 | * 01 Channel 1 (5)
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73 | * 10 Channel 2 (6)
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74 | * 11 Channel 3 (7)
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75 | *
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76 | *
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77 | */
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78 | |||
79 | #include <sys/cdefs.h> |
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80 | #include <driver.h> |
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81 | #include <cpufunc.h> |
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82 | |||
83 | #ifdef DEBUG
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84 | #define DPRINTF(a) printf a
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85 | #else
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86 | #define DPRINTF(a)
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87 | #endif
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88 | |||
89 | #define NR_DMAS 8 |
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90 | |||
91 | #define DMA_MAX (1024 * 64) |
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92 | #define DMA_MASK (DMA_MAX-1) |
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93 | #define DMA_ALIGN(n) ((((paddr_t)(n)) + DMA_MASK) & ~DMA_MASK)
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94 | |||
95 | void dma_stop(dma_t handle);
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96 | static int dma_init(struct driver *self); |
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97 | |||
98 | |||
99 | /*
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100 | * DMA descriptor
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101 | */
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102 | struct dma {
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103 | int chan; /* dma channel */ |
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104 | int in_use; /* true if used */ |
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105 | }; |
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106 | |||
107 | /*
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108 | * DMA i/o port
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109 | */
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110 | struct dma_port {
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111 | int mask;
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112 | int mode;
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113 | int clear;
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114 | int addr;
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115 | int count;
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116 | int page;
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117 | }; |
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118 | |||
119 | static const struct dma_port dma_regs[] = { |
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120 | /* mask, mode, clear, addr, count, page */
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121 | {0x0a, 0x0b, 0x0c, 0x00, 0x01, 0x87}, /* Channel 0 */ |
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122 | {0x0a, 0x0b, 0x0c, 0x02, 0x03, 0x83}, /* Channel 1 */ |
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123 | {0x0a, 0x0b, 0x0c, 0x04, 0x05, 0x81}, /* Channel 2 */ |
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124 | {0x0a, 0x0b, 0x0c, 0x06, 0x07, 0x82}, /* Channel 3 */ |
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125 | {0xd4, 0xd6, 0xd8, 0xc0, 0xc2, 0x8f}, /* Channel 4 (n/a) */ |
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126 | {0xd4, 0xd6, 0xd8, 0xc4, 0xc6, 0x8b}, /* Channel 5 */ |
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127 | {0xd4, 0xd6, 0xd8, 0xc8, 0xca, 0x89}, /* Channel 6 */ |
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128 | {0xd4, 0xd6, 0xd8, 0xcc, 0xce, 0x8a}, /* Channel 7 */ |
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129 | }; |
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130 | |||
131 | static struct dma dma_table[NR_DMAS]; |
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132 | |||
133 | struct driver i8237_driver = {
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134 | /* name */ "dma", |
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135 | /* devsops */ NULL, |
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136 | /* devsz */ 0, |
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137 | /* flags */ 0, |
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138 | /* probe */ NULL, |
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139 | /* init */ dma_init,
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140 | /* shutdown */ NULL, |
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141 | }; |
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142 | |||
143 | |||
144 | /*
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145 | * Attach dma.
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146 | * Return dma handle on success, or panic on failure.
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147 | * DMA4 can not be used with pc.
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148 | */
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149 | dma_t |
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150 | dma_attach(int chan)
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151 | { |
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152 | struct dma *dma;
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153 | int s;
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154 | |||
155 | ASSERT(chan >= 0 && chan < NR_DMAS);
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156 | ASSERT(chan != 4);
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157 | DPRINTF(("DMA%d attached\n", chan));
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158 | |||
159 | s = splhigh(); |
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160 | dma = &dma_table[chan]; |
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161 | if (dma->in_use) {
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162 | panic("dma_attach");
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163 | } else {
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164 | dma->chan = chan; |
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165 | dma->in_use = 1;
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166 | } |
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167 | dma_stop((dma_t)dma); |
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168 | splx(s); |
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169 | return (dma_t)dma;
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170 | } |
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171 | |||
172 | /*
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173 | * Detach dma.
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174 | */
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175 | void
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176 | dma_detach(dma_t handle) |
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177 | { |
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178 | struct dma *dma = (struct dma *)handle; |
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179 | int s;
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180 | |||
181 | ASSERT(dma->in_use); |
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182 | DPRINTF(("DMA%d detached\n", dma->chan));
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183 | |||
184 | s = splhigh(); |
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185 | dma->in_use = 0;
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186 | splx(s); |
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187 | } |
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188 | |||
189 | void
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190 | dma_setup(dma_t handle, void *addr, u_long count, int read) |
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191 | { |
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192 | struct dma *dma = (struct dma *)handle; |
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193 | const struct dma_port *regs; |
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194 | u_int chan, bits, mode; |
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195 | paddr_t paddr; |
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196 | int s;
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197 | |||
198 | ASSERT(handle); |
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199 | paddr = kvtop(addr); |
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200 | |||
201 | /* dma address must be under 16M. */
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202 | ASSERT(paddr < 0xffffff);
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203 | |||
204 | s = splhigh(); |
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205 | |||
206 | chan = (u_int)dma->chan; |
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207 | regs = &dma_regs[chan]; |
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208 | bits = (chan < 4) ? chan : chan >> 2; |
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209 | mode = read ? 0x44U : 0x48U; |
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210 | count--; |
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211 | |||
212 | bus_write_8(regs->mask, bits | 0x04); /* Disable channel */ |
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213 | bus_write_8(regs->clear, 0x00); /* Clear byte pointer flip-flop */ |
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214 | bus_write_8(regs->mode, bits | mode); /* Set mode */
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215 | bus_write_8(regs->addr, (u_char)((paddr >> 0) & 0xff)); /* Address low */ |
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216 | bus_write_8(regs->addr, (u_char)((paddr >> 8) & 0xff)); /* Address high */ |
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217 | bus_write_8(regs->page, (u_char)((paddr >> 16) & 0xff)); /* Page address */ |
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218 | bus_write_8(regs->clear, 0x00); /* Clear byte pointer flip-flop */ |
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219 | bus_write_8(regs->count, (u_char)((count >> 0) & 0xff)); /* Count low */ |
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220 | bus_write_8(regs->count, (u_char)((count >> 8) & 0xff)); /* Count high */ |
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221 | bus_write_8(regs->mask, bits); /* Enable channel */
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222 | |||
223 | splx(s); |
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224 | } |
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225 | |||
226 | void
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227 | dma_stop(dma_t handle) |
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228 | { |
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229 | struct dma *dma = (struct dma *)handle; |
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230 | u_int chan; |
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231 | u_int bits; |
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232 | int s;
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233 | |||
234 | ASSERT(handle); |
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235 | s = splhigh(); |
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236 | chan = (u_int)dma->chan; |
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237 | |||
238 | bits = (chan < 4) ? chan : chan >> 2; |
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239 | bus_write_8(dma_regs[chan].mask, bits | 0x04); /* Disable channel */ |
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240 | splx(s); |
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241 | } |
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242 | |||
243 | /*
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244 | * Allocate DMA buffer
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245 | *
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246 | * Return page address in 64K byte boundary.
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247 | * The caller must deallocate the pages by using page_free().
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248 | */
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249 | void *
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250 | dma_alloc(size_t size) |
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251 | { |
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252 | paddr_t tmp, base; |
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253 | |||
254 | if (size > DMA_MAX)
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255 | return NULL; |
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256 | |||
257 | sched_lock(); |
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258 | |||
259 | /*
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260 | * Try to allocate temporary buffer for enough size (64K + size).
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261 | */
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262 | size = round_page(size); |
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263 | tmp = page_alloc((size_t)(DMA_MAX + size)); |
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264 | if (tmp == 0) { |
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265 | sched_unlock(); |
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266 | return NULL; |
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267 | } |
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268 | page_free(tmp, (size_t)(DMA_MAX + size)); |
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269 | |||
270 | /*
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271 | * Now, we know the free address with 64k boundary.
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272 | */
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273 | base = DMA_ALIGN(tmp); |
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274 | page_reserve(base, size); |
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275 | |||
276 | sched_unlock(); |
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277 | return ptokv(base);
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278 | } |
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279 | |||
280 | static int |
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281 | dma_init(struct driver *self)
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282 | { |
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283 | |||
284 | return 0; |
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285 | } |