root / prex-0.9.0 / bsp / boot / x86 / pc / debug.c @ 03e9c04a
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1 | 03e9c04a | Brad Neuman | /*-
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2 | * Copyright (c) 2005-2009, Kohsuke Ohtani
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3 | * All rights reserved.
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4 | *
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5 | * Redistribution and use in source and binary forms, with or without
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6 | * modification, are permitted provided that the following conditions
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7 | * are met:
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8 | * 1. Redistributions of source code must retain the above copyright
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9 | * notice, this list of conditions and the following disclaimer.
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10 | * 2. Redistributions in binary form must reproduce the above copyright
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11 | * notice, this list of conditions and the following disclaimer in the
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12 | * documentation and/or other materials provided with the distribution.
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13 | * 3. Neither the name of the author nor the names of any co-contributors
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14 | * may be used to endorse or promote products derived from this software
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15 | * without specific prior written permission.
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16 | *
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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27 | * SUCH DAMAGE.
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28 | */
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29 | |||
30 | #include <sys/param.h> |
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31 | #include <boot.h> |
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32 | |||
33 | extern void outb(int, u_char); |
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34 | extern u_char inb(int); |
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35 | |||
36 | #define SCREEN_80x25 1 |
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37 | /* #define SCREEN_80x50 1 */
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38 | |||
39 | #define COM_BASE CONFIG_NS16550_BASE
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40 | |||
41 | /* Register offsets */
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42 | #define COM_RBR (COM_BASE + 0x00) /* receive buffer register */ |
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43 | #define COM_THR (COM_BASE + 0x00) /* transmit holding register */ |
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44 | #define COM_IER (COM_BASE + 0x01) /* interrupt enable register */ |
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45 | #define COM_FCR (COM_BASE + 0x02) /* FIFO control register */ |
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46 | #define COM_IIR (COM_BASE + 0x02) /* interrupt identification register */ |
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47 | #define COM_LCR (COM_BASE + 0x03) /* line control register */ |
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48 | #define COM_MCR (COM_BASE + 0x04) /* modem control register */ |
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49 | #define COM_LSR (COM_BASE + 0x05) /* line status register */ |
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50 | #define COM_MSR (COM_BASE + 0x06) /* modem status register */ |
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51 | #define COM_DLL (COM_BASE + 0x00) /* divisor latch LSB (LCR[7] = 1) */ |
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52 | #define COM_DLM (COM_BASE + 0x01) /* divisor latch MSB (LCR[7] = 1) */ |
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53 | |||
54 | /*
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55 | * Print one chracter
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56 | */
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57 | void
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58 | debug_putc(int c)
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59 | { |
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60 | |||
61 | #if defined(DEBUG) && defined(CONFIG_DIAG_SERIAL)
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62 | /*
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63 | * output to serial port.
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64 | */
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65 | while (!(inb(COM_LSR) & 0x20)) |
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66 | ; |
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67 | outb(COM_THR, c); |
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68 | #endif
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69 | |||
70 | #if defined(DEBUG) && defined(CONFIG_DIAG_BOCHS)
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71 | /*
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72 | * output to bochs emulater console.
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73 | */
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74 | if (inb(0xe9) == 0xe9) |
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75 | outb(0xe9, (u_char)c);
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76 | #endif
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77 | } |
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78 | |||
79 | /*
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80 | * Initialize debug port.
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81 | */
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82 | void
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83 | debug_init(void)
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84 | { |
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85 | |||
86 | #if defined(DEBUG) && defined(CONFIG_DIAG_SERIAL)
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87 | /*
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88 | * Initialize serial port.
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89 | */
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90 | if (inb(COM_LSR) == 0xff) |
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91 | return; /* Serial port is disabled */ |
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92 | |||
93 | outb(COM_IER, 0x00); /* Disable interrupt */ |
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94 | outb(COM_LCR, 0x80); /* Access baud rate */ |
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95 | outb(COM_DLL, 0x01); /* 115200 baud */ |
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96 | outb(COM_DLM, 0x00);
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97 | outb(COM_LCR, 0x03); /* N, 8, 1 */ |
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98 | outb(COM_MCR, 0x03); /* Ready */ |
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99 | outb(COM_FCR, 0x00); /* Disable FIFO */ |
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100 | inb(COM_RBR); |
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101 | inb(COM_RBR); |
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102 | #endif
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103 | } |