scoutos / prex-0.9.0 / bsp / hal / x86 / pc / interrupt.c @ 03e9c04a
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/*-
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* Copyright (c) 2005-2007, Kohsuke Ohtani
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* interrupt.c - interrupt management routines for intel 8259 chip
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*/
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#include <sys/ipl.h> |
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#include <kernel.h> |
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#include <irq.h> |
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#include <cpufunc.h> |
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#include <context.h> |
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#include <locore.h> |
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#include <hal.h> |
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/* Number of IRQ lines */
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#define NIRQS 16 |
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/* I/O address for master/slave programmable interrupt controller */
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#define PIC_M 0x20 |
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#define PIC_S 0xa0 |
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/* Edge/level control register */
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#define ELCR 0x4d0 |
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/*
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* Interrupt priority level
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*
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* Each interrupt has its logical priority level, with 0 being
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* the highest priority. While some ISR is running, all lower
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* priority interrupts are masked off.
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*/
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static volatile int irq_level; |
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/*
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* Interrupt mapping table
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*/
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static int ipl_table[NIRQS]; /* Vector -> level */ |
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static u_int mask_table[NIPLS]; /* Level -> mask */ |
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/*
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* Set mask for current ipl
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*/
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static void |
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update_mask(void)
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{ |
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u_int mask = mask_table[irq_level]; |
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outb(PIC_M + 1, mask & 0xff); |
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outb(PIC_S + 1, mask >> 8); |
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} |
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/*
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* Unmask interrupt in PIC for specified irq.
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* The interrupt mask table is also updated.
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* Assumed CPU interrupt is disabled in caller.
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*/
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void
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interrupt_unmask(int vector, int level) |
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{ |
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u_int unmask = (u_int)~(1 << vector);
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int i, s;
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s = splhigh(); |
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ipl_table[vector] = level; |
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/*
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* Unmask target interrupt for all
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* lower interrupt levels.
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*/
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for (i = 0; i < level; i++) |
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mask_table[i] &= unmask; |
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update_mask(); |
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splx(s); |
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} |
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/*
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* Mask interrupt in PIC for specified irq.
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* Interrupt must be disabled when this routine is called.
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*/
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void
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interrupt_mask(int vector)
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{ |
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u_int mask = (u_int)(1 << vector);
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int i, level, s;
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s = splhigh(); |
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level = ipl_table[vector]; |
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for (i = 0; i < level; i++) |
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mask_table[i] |= mask; |
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ipl_table[vector] = IPL_NONE; |
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update_mask(); |
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splx(s); |
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} |
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/*
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* Setup interrupt mode.
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* Select whether an interrupt trigger is edge or level.
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*/
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void
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interrupt_setup(int vector, int mode) |
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{ |
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int port, s;
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u_int bit; |
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u_char val; |
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s = splhigh(); |
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port = vector < 8 ? ELCR : ELCR + 1; |
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bit = (u_int)(1 << (vector & 7)); |
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val = inb(port); |
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if (mode == IMODE_LEVEL)
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val |= bit; |
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else
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val &= ~bit; |
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outb(port, val); |
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splx(s); |
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} |
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/*
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* Common interrupt handler.
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*
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* This routine is called from the low level interrupt routine
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* written in assemble code. The interrupt flag is automatically
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* disabled by h/w in CPU when the interrupt is occurred. The
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* target interrupt will be masked in ICU while the irq handler
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* is called.
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*/
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void
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interrupt_handler(struct cpu_regs *regs)
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{ |
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int vector = (int)regs->trap_no; |
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int old_ipl, new_ipl;
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/* Adjust interrupt level */
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old_ipl = irq_level; |
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new_ipl = ipl_table[vector]; |
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if (new_ipl > old_ipl) /* Ignore spurious interrupt */ |
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irq_level = new_ipl; |
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update_mask(); |
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/* Send acknowledge to PIC for specified irq */
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if (vector & 8) /* Slave ? */ |
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outb(PIC_S, 0x20); /* Non specific EOI to slave */ |
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outb(PIC_M, 0x20); /* Non specific EOI to master */ |
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/* Dispatch interrupt */
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splon(); |
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irq_handler(vector); |
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sploff(); |
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/* Restore interrupt level */
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irq_level = old_ipl; |
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update_mask(); |
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} |
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/*
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* Initialize 8259 interrupt controllers.
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* All interrupts will be masked off in ICU.
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*/
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void
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interrupt_init(void)
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{ |
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int i;
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irq_level = IPL_NONE; |
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for (i = 0; i < NIRQS; i++) |
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ipl_table[i] = IPL_NONE; |
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for (i = 0; i < NIPLS; i++) |
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mask_table[i] = 0xfffb;
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outb_p(PIC_M, 0x11); /* Start initialization edge, master */ |
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outb_p(PIC_M + 1, 0x20); /* Set h/w vector = 0x20 */ |
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outb_p(PIC_M + 1, 0x04); /* Chain to slave (IRQ2) */ |
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outb_p(PIC_M + 1, 0x01); /* 8086 mode */ |
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outb_p(PIC_S, 0x11); /* Start initialization edge, master */ |
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outb_p(PIC_S + 1, 0x28); /* Set h/w vector = 0x28 */ |
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outb_p(PIC_S + 1, 0x02); /* Slave (cascade) */ |
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outb_p(PIC_S + 1, 0x01); /* 8086 mode */ |
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outb(PIC_S + 1, 0xff); /* Mask all */ |
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outb(PIC_M + 1, 0xfb); /* Mask all except IRQ2 (cascade) */ |
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} |