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scoutos / prex-0.9.0 / bsp / drv / dev / dma / i8237.c @ 03e9c04a

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/*-
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 * Copyright (c) 2005, Kohsuke Ohtani
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * 1. Redistributions of source code must retain the above copyright
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 *    notice, this list of conditions and the following disclaimer.
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 * 2. Redistributions in binary form must reproduce the above copyright
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 *    notice, this list of conditions and the following disclaimer in the
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 *    documentation and/or other materials provided with the distribution.
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 * 3. Neither the name of the author nor the names of any co-contributors
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 *    may be used to endorse or promote products derived from this software
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 *    without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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 * SUCH DAMAGE.
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 */
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/*
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 * i8237.c - Intel 8237 DMA controller
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 */
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/**
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 *  Memo:
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 *
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 *  [Mode Register]
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 *
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 *      Bits     Function
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 *      -------- Mode Selection
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 *      00          Demand Mode
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 *      01          Single Mode
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 *      10          Block Mode
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 *      11          Cascade Mode
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 *      -------- Address Increment/Decrement
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 *        1         Address Decrement
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 *        0         Address Increment
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 *      -------- Auto-Initialization Enable
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 *         1        Auto-Initialization DMA
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 *         0        Single-Cycle DMA
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 *      -------- Transfer Type
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 *          00      Verify
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 *          01      Write
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 *          10      Read
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 *          11      Illegal
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 *      -------- Channel Selection
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 *            00    Channel 0 (4)
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 *            01    Channel 1 (5)
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 *            10    Channel 2 (6)
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 *            11    Channel 3 (7)
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 *
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 *  [Single Mask Register]
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 *
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 *      Bits     Function
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 *      --------
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 *      00000    Unused, Set to 0
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 *      -------- Set/Clear Mask
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 *           1      Set (Disable Channel)
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 *           0      Clear (Enable Channel)
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 *      -------- Channel Selection
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 *            00    Channel 0 (4)
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 *            01    Channel 1 (5)
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 *            10    Channel 2 (6)
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 *            11    Channel 3 (7)
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 *
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 *
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 */
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#include <sys/cdefs.h>
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#include <driver.h>
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#include <cpufunc.h>
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#ifdef DEBUG
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#define DPRINTF(a) printf a
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#else
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#define DPRINTF(a)
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#endif
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#define NR_DMAS                8
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#define DMA_MAX                (1024 * 64)
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#define DMA_MASK        (DMA_MAX-1)
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#define DMA_ALIGN(n)        ((((paddr_t)(n)) + DMA_MASK) & ~DMA_MASK)
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void                dma_stop(dma_t handle);
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static int        dma_init(struct driver *self);
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/*
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 * DMA descriptor
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 */
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struct dma {
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        int        chan;                /* dma channel */
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        int        in_use;                /* true if used */
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};
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/*
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 * DMA i/o port
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 */
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struct dma_port {
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        int        mask;
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        int        mode;
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        int        clear;
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        int        addr;
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        int        count;
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        int        page;
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};
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static const struct dma_port dma_regs[] = {
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/*        mask,  mode,  clear, addr,  count, page */
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        {0x0a, 0x0b, 0x0c, 0x00, 0x01, 0x87},        /* Channel 0 */
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        {0x0a, 0x0b, 0x0c, 0x02, 0x03, 0x83},        /* Channel 1 */
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        {0x0a, 0x0b, 0x0c, 0x04, 0x05, 0x81},        /* Channel 2 */
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        {0x0a, 0x0b, 0x0c, 0x06, 0x07, 0x82},        /* Channel 3 */
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        {0xd4, 0xd6, 0xd8, 0xc0, 0xc2, 0x8f},        /* Channel 4 (n/a) */
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        {0xd4, 0xd6, 0xd8, 0xc4, 0xc6, 0x8b},        /* Channel 5 */
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        {0xd4, 0xd6, 0xd8, 0xc8, 0xca, 0x89},        /* Channel 6 */
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        {0xd4, 0xd6, 0xd8, 0xcc, 0xce, 0x8a},        /* Channel 7 */
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};
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static struct dma dma_table[NR_DMAS];
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struct driver i8237_driver = {
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        /* name */        "dma",
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        /* devsops */        NULL,
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        /* devsz */        0,
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        /* flags */        0,
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        /* probe */        NULL,
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        /* init */        dma_init,
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        /* shutdown */        NULL,
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};
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/*
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 * Attach dma.
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 * Return dma handle on success, or panic on failure.
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 * DMA4 can not be used with pc.
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 */
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dma_t
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dma_attach(int chan)
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{
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        struct dma *dma;
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        int s;
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        ASSERT(chan >= 0 && chan < NR_DMAS);
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        ASSERT(chan != 4);
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        DPRINTF(("DMA%d attached\n", chan));
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        s = splhigh();
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        dma = &dma_table[chan];
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        if (dma->in_use) {
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                panic("dma_attach");
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        } else {
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                dma->chan = chan;
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                dma->in_use = 1;
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        }
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        dma_stop((dma_t)dma);
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        splx(s);
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        return (dma_t)dma;
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}
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/*
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 * Detach dma.
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 */
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void
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dma_detach(dma_t handle)
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{
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        struct dma *dma = (struct dma *)handle;
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        int s;
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        ASSERT(dma->in_use);
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        DPRINTF(("DMA%d detached\n", dma->chan));
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        s = splhigh();
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        dma->in_use = 0;
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        splx(s);
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}
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void
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dma_setup(dma_t handle, void *addr, u_long count, int read)
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{
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        struct dma *dma = (struct dma *)handle;
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        const struct dma_port *regs;
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        u_int chan, bits, mode;
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        paddr_t paddr;
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        int s;
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        ASSERT(handle);
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        paddr = kvtop(addr);
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        /* dma address must be under 16M. */
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        ASSERT(paddr < 0xffffff);
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        s = splhigh();
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        chan = (u_int)dma->chan;
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        regs = &dma_regs[chan];
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        bits = (chan < 4) ? chan : chan >> 2;
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        mode = read ? 0x44U : 0x48U;
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        count--;
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        bus_write_8(regs->mask, bits | 0x04);        /* Disable channel */
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        bus_write_8(regs->clear, 0x00);                /* Clear byte pointer flip-flop */
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        bus_write_8(regs->mode, bits | mode);        /* Set mode */
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        bus_write_8(regs->addr, (u_char)((paddr >> 0) & 0xff));        /* Address low */
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        bus_write_8(regs->addr, (u_char)((paddr >> 8) & 0xff));        /* Address high */
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        bus_write_8(regs->page, (u_char)((paddr >> 16) & 0xff));        /* Page address */
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        bus_write_8(regs->clear, 0x00);                /* Clear byte pointer flip-flop */
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        bus_write_8(regs->count, (u_char)((count >> 0) & 0xff));        /* Count low */
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        bus_write_8(regs->count, (u_char)((count >> 8) & 0xff));        /* Count high */
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        bus_write_8(regs->mask, bits);                /* Enable channel */
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        splx(s);
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}
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void
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dma_stop(dma_t handle)
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{
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        struct dma *dma = (struct dma *)handle;
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        u_int chan;
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        u_int bits;
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        int s;
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        ASSERT(handle);
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        s = splhigh();
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        chan = (u_int)dma->chan;
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        bits = (chan < 4) ? chan : chan >> 2;
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        bus_write_8(dma_regs[chan].mask, bits | 0x04);        /* Disable channel */
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        splx(s);
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}
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/*
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 * Allocate DMA buffer
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 *
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 * Return page address in 64K byte boundary.
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 * The caller must deallocate the pages by using page_free().
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 */
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void *
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dma_alloc(size_t size)
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{
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        paddr_t tmp, base;
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        if (size > DMA_MAX)
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                return NULL;
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        sched_lock();
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        /*
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         * Try to allocate temporary buffer for enough size (64K + size).
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         */
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        size = round_page(size);
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        tmp = page_alloc((size_t)(DMA_MAX + size));
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        if (tmp == 0) {
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                sched_unlock();
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                return NULL;
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        }
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        page_free(tmp, (size_t)(DMA_MAX + size));
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        /*
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         * Now, we know the free address with 64k boundary.
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         */
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        base = DMA_ALIGN(tmp);
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        page_reserve(base, size);
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        sched_unlock();
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        return ptokv(base);
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}
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static int
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dma_init(struct driver *self)
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{
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        return 0;
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}