scoutos / prex-0.9.0 / bsp / hal / arm / gba / interrupt.c @ 03e9c04a
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1 | 03e9c04a | Brad Neuman | /*-
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2 | * Copyright (c) 2005-2007, Kohsuke Ohtani
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3 | * All rights reserved.
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4 | *
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5 | * Redistribution and use in source and binary forms, with or without
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6 | * modification, are permitted provided that the following conditions
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7 | * are met:
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8 | * 1. Redistributions of source code must retain the above copyright
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9 | * notice, this list of conditions and the following disclaimer.
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10 | * 2. Redistributions in binary form must reproduce the above copyright
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11 | * notice, this list of conditions and the following disclaimer in the
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12 | * documentation and/or other materials provided with the distribution.
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13 | * 3. Neither the name of the author nor the names of any co-contributors
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14 | * may be used to endorse or promote products derived from this software
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15 | * without specific prior written permission.
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16 | *
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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27 | * SUCH DAMAGE.
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28 | */
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29 | |||
30 | /*
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31 | * interrupt.c - interrupt handling routines for GBA
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32 | */
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33 | |||
34 | #include <sys/ipl.h> |
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35 | #include <kernel.h> |
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36 | #include <hal.h> |
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37 | #include <irq.h> |
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38 | #include <locore.h> |
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39 | #include <cpufunc.h> |
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40 | #include <context.h> |
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41 | |||
42 | /* Number of IRQ lines */
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43 | #define NIRQS 14 |
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44 | |||
45 | /* Interrupt hook vector */
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46 | #define IRQ_VECTOR *(uint32_t *)0x3007ffc |
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47 | |||
48 | /* Registers for interrupt control unit - enable/flag/master */
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49 | #define ICU_IE (*(volatile uint16_t *)0x4000200) |
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50 | #define ICU_IF (*(volatile uint16_t *)0x4000202) |
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51 | #define ICU_IME (*(volatile uint16_t *)0x4000208) |
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52 | |||
53 | /* ICU_IE */
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54 | #define IRQ_VALID 0x3fff |
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55 | |||
56 | /* ICU_IME */
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57 | #define IRQ_OFF 0 |
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58 | #define IRQ_ON 1 |
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59 | |||
60 | /*
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61 | * Interrupt priority level
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62 | *
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63 | * Each interrupt has its logical priority level, with 0 being
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64 | * the lowest priority. While some ISR is running, all lower
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65 | * priority interrupts are masked off.
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66 | */
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67 | volatile int irq_level; |
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68 | |||
69 | /*
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70 | * Interrupt mapping table
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71 | */
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72 | static int ipl_table[NIRQS]; /* Vector -> level */ |
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73 | static uint16_t mask_table[NIPLS]; /* Level -> mask */ |
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74 | |||
75 | /*
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76 | * Set mask for current ipl
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77 | */
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78 | #define update_mask() ICU_IE = mask_table[irq_level]
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79 | |||
80 | /*
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81 | * Unmask interrupt in PIC for specified irq.
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82 | * The interrupt mask table is also updated.
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83 | * Assumes CPU interrupt is disabled in caller.
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84 | */
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85 | void
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86 | interrupt_unmask(int vector, int level) |
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87 | { |
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88 | int i;
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89 | uint16_t unmask = (uint16_t)1 << vector;
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90 | |||
91 | /* Save level mapping */
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92 | ipl_table[vector] = level; |
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93 | |||
94 | /*
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95 | * Unmask target interrupt for all
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96 | * lower interrupt levels.
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97 | */
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98 | for (i = 0; i < level; i++) |
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99 | mask_table[i] |= unmask; |
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100 | update_mask(); |
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101 | } |
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102 | |||
103 | /*
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104 | * Mask interrupt in PIC for specified irq.
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105 | * Interrupt must be disabled when this routine is called.
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106 | */
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107 | void
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108 | interrupt_mask(int vector)
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109 | { |
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110 | int i, level;
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111 | u_int mask = (uint16_t)~(1 << vector);
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112 | |||
113 | level = ipl_table[vector]; |
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114 | for (i = 0; i < level; i++) |
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115 | mask_table[i] &= mask; |
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116 | ipl_table[vector] = IPL_NONE; |
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117 | update_mask(); |
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118 | } |
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119 | |||
120 | /*
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121 | * Setup interrupt mode.
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122 | * Select whether an interrupt trigger is edge or level.
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123 | */
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124 | void
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125 | interrupt_setup(int vector, int mode) |
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126 | { |
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127 | /* nop */
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128 | } |
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129 | |||
130 | /*
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131 | * Dispatch interrupt
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132 | */
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133 | void
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134 | interrupt_dispatch(int vector)
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135 | { |
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136 | int old_ipl;
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137 | |||
138 | /* Save & update interrupt level */
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139 | old_ipl = irq_level; |
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140 | irq_level = ipl_table[vector]; |
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141 | update_mask(); |
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142 | |||
143 | /* Send acknowledge to ICU for this irq */
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144 | ICU_IF = (uint16_t)(1 << vector);
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145 | |||
146 | /* Allow another interrupt that has higher priority */
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147 | splon(); |
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148 | |||
149 | /* Dispatch interrupt */
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150 | irq_handler(vector); |
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151 | |||
152 | sploff(); |
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153 | |||
154 | /* Restore interrupt level */
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155 | irq_level = old_ipl; |
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156 | update_mask(); |
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157 | } |
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158 | |||
159 | /*
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160 | * Common interrupt handler.
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161 | */
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162 | void
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163 | interrupt_handler(void)
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164 | { |
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165 | uint16_t bits; |
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166 | int vector;
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167 | |||
168 | bits = ICU_IF; |
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169 | retry:
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170 | for (vector = 0; vector < NIRQS; vector++) { |
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171 | if (bits & (uint16_t)(1 << vector)) |
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172 | break;
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173 | } |
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174 | if (vector == NIRQS)
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175 | goto out;
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176 | |||
177 | interrupt_dispatch(vector); |
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178 | |||
179 | /*
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180 | * Multiple interrupts can be fired in case of GBA.
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181 | * So, we have to check the interrupt status, again.
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182 | */
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183 | bits = ICU_IF; |
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184 | if (bits & IRQ_VALID)
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185 | goto retry;
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186 | out:
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187 | return;
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188 | } |
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189 | |||
190 | /*
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191 | * Initialize interrupt controllers.
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192 | * All interrupts will be masked off.
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193 | */
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194 | void
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195 | interrupt_init(void)
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196 | { |
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197 | int i;
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198 | |||
199 | irq_level = IPL_NONE; |
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200 | |||
201 | for (i = 0; i < NIRQS; i++) |
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202 | ipl_table[i] = IPL_NONE; |
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203 | |||
204 | for (i = 0; i < NIPLS; i++) |
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205 | mask_table[i] = 0;
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206 | |||
207 | ICU_IME = IRQ_OFF; |
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208 | |||
209 | /*
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210 | * Since GBA has its own interrupt vector in ROM area,
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211 | * we can not modify it. Instead, the GBA BIOS will
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212 | * call the user's interrupt hook routine placed in
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213 | * the address in 0x3007ffc.
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214 | */
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215 | IRQ_VECTOR = (uint32_t)interrupt_entry; /* Interrupt hook address */
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216 | ICU_IE = 0; /* Mask all interrupts */ |
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217 | ICU_IME = IRQ_ON; |
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218 | } |