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sim-outorder: SimpleScalar/PISA Tool Set version 3.0 of September, 1998.
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Copyright (c) 1994-1998 by Todd M. Austin.  All Rights Reserved.
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Processor Parameters:
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Issue Width: 4
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Window Size: 16
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Number of Virtual Registers: 32
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Number of Physical Registers: 16
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Datapath Width: 64
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Total Power Consumption: 24.105
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Branch Predictor Power Consumption: 1.14342  (5.17%)
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 branch target buffer power (W): 1.04097
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 local predict power (W): 0.0275244
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 global predict power (W): 0.031332
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 chooser power (W): 0.0206036
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 RAS power (W): 0.0229956
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Rename Logic Power Consumption: 0.0887797  (0.402%)
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 Instruction Decode Power (W): 0.0038821
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 RAT decode_power (W): 0.0273861
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 RAT wordline_power (W): 0.00645964
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 RAT bitline_power (W): 0.0486255
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 DCL Comparators (W): 0.0024263
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Instruction Window Power Consumption: 0.517536  (2.34%)
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 tagdrive (W): 0.0186418
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 tagmatch (W): 0.00697769
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 Selection Logic (W): 0.00331194
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 decode_power (W): 0.0131921
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 wordline_power (W): 0.0176803
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 bitline_power (W): 0.457732
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Load/Store Queue Power Consumption: 0.201758  (0.913%)
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 tagdrive (W): 0.0854673
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 tagmatch (W): 0.0207657
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 decode_power (W): 0.00194105
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 wordline_power (W): 0.00302882
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 bitline_power (W): 0.0905553
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Arch. Register File Power Consumption: 0.769909  (3.48%)
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 decode_power (W): 0.0273861
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 wordline_power (W): 0.0176803
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 bitline_power (W): 0.724843
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Result Bus Power Consumption: 0.499392  (2.26%)
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Total Clock Power: 10.1199  (45.8%)
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Int ALU Power: 1.19732  (5.42%)
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FP ALU Power: 3.66922  (16.6%)
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Instruction Cache Power Consumption: 0.614638  (2.78%)
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 decode_power (W): 0.186809
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 wordline_power (W): 0.00542611
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 bitline_power (W): 0.231588
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 senseamp_power (W): 0.07296
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 tagarray_power (W): 0.117856
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Itlb_power (W): 0.0565504 (0.256%)
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Data Cache Power Consumption: 1.80232  (8.15%)
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 decode_power (W): 0.15387
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 wordline_power (W): 0.0368784
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 bitline_power (W): 0.749615
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 senseamp_power (W): 0.58368
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 tagarray_power (W): 0.278274
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Dtlb_power (W): 0.193103 (0.874%)
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Level 2 Cache Power Consumption: 1.23116 (5.57%)
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 decode_power (W): 0.0990259
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 wordline_power (W): 0.00799512
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 bitline_power (W): 0.83087
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 senseamp_power (W): 0.14592
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 tagarray_power (W): 0.147353
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sim: command line: ./sim-outorder -max:inst 10000000 gcc00.O2unroll.gcc.100M.ss -funroll-loops -fforce-mem -fcse-follow-jumps -fcse-skip-blocks -fexpensive-optimizations -fstrength-reduce -fpeephole -fschedule-insns -finline-functions -fschedule-insns2 -O regclass.i -o regclass.s 
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sim: simulation started @ Tue Dec  1 19:35:03 2009, options follow:
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sim-outorder: This simulator implements a very detailed out-of-order issue
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superscalar processor with a two-level memory system and speculative
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execution support.  This simulator is a performance simulator, tracking the
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latency of all pipeline operations.
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# -config                     # load configuration from a file
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# -dumpconfig                 # dump configuration to a file
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# -h                    false # print help message    
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# -v                    false # verbose operation     
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# -d                    false # enable debug message  
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# -i                    false # start in Dlite debugger
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-seed                       1 # random number generator seed (0 for timer seed)
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# -q                    false # initialize and terminate immediately
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# -chkpt               <null> # restore EIO trace execution from <fname>
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# -redir:sim           <null> # redirect simulator output to file (non-interactive only)
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# -redir:prog          <null> # redirect simulated program output to file
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-nice                       0 # simulator scheduling priority
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-max:inst            10000000 # maximum number of inst's to execute
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-fastfwd                    0 # number of insts skipped before timing starts
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# -ptrace              <null> # generate pipetrace, i.e., <fname|stdout|stderr> <range>
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-fetch:ifqsize              4 # instruction fetch queue size (in insts)
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-fetch:mplat                3 # extra branch mis-prediction latency
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-fetch:speed                1 # speed of front-end of machine relative to execution core
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-bpred                  bimod # branch predictor type {nottaken|taken|perfect|bimod|2lev|comb}
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-bpred:bimod     2048 # bimodal predictor config (<table size>)
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-bpred:2lev      1 1024 8 0 # 2-level predictor config (<l1size> <l2size> <hist_size> <xor>)
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-bpred:comb      1024 # combining predictor config (<meta_table_size>)
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-bpred:ras                  8 # return address stack size (0 for no return stack)
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-bpred:btb       512 4 # BTB config (<num_sets> <associativity>)
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# -bpred:spec_update       <null> # speculative predictors update in {ID|WB} (default non-spec)
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-decode:width               4 # instruction decode B/W (insts/cycle)
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-issue:width                4 # instruction issue B/W (insts/cycle)
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-issue:inorder          false # run pipeline with in-order issue
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-issue:wrongpath         true # issue instructions down wrong execution paths
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-commit:width               4 # instruction commit B/W (insts/cycle)
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-ruu:size                  16 # register update unit (RUU) size
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-lsq:size                   8 # load/store queue (LSQ) size
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-cache:dl1       dl1:128:32:4:l # l1 data cache config, i.e., {<config>|none}
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-cache:dl1lat               1 # l1 data cache hit latency (in cycles)
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-cache:dl2       ul2:1024:64:4:l # l2 data cache config, i.e., {<config>|none}
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-cache:dl2lat               6 # l2 data cache hit latency (in cycles)
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-cache:il1       il1:512:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2|none}
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-cache:il1lat               1 # l1 instruction cache hit latency (in cycles)
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-cache:il2                dl2 # l2 instruction cache config, i.e., {<config>|dl2|none}
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-cache:il2lat               6 # l2 instruction cache hit latency (in cycles)
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-cache:flush            false # flush caches on system calls
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-cache:icompress        false # convert 64-bit inst addresses to 32-bit inst equivalents
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-mem:lat         18 2 # memory access latency (<first_chunk> <inter_chunk>)
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-mem:width                  8 # memory access bus width (in bytes)
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-tlb:itlb        itlb:16:4096:4:l # instruction TLB config, i.e., {<config>|none}
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-tlb:dtlb        dtlb:32:4096:4:l # data TLB config, i.e., {<config>|none}
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-tlb:lat                   30 # inst/data TLB miss latency (in cycles)
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-res:ialu                   4 # total number of integer ALU's available
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-res:imult                  1 # total number of integer multiplier/dividers available
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-res:memport                2 # total number of memory system ports available (to CPU)
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-res:fpalu                  4 # total number of floating point ALU's available
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-res:fpmult                 1 # total number of floating point multiplier/dividers available
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# -pcstat              <null> # profile stat(s) against text addr's (mult uses ok)
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-bugcompat              false # operate in backward-compatible bugs mode (for testing only)
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  Pipetrace range arguments are formatted as follows:
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    {{@|#}<start>}:{{@|#|+}<end>}
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  Both ends of the range are optional, if neither are specified, the entire
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  execution is traced.  Ranges that start with a `@' designate an address
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  range to be traced, those that start with an `#' designate a cycle count
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  range.  All other range values represent an instruction count range.  The
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  second argument, if specified with a `+', indicates a value relative
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  to the first argument, e.g., 1000:+100 == 1000:1100.  Program symbols may
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  be used in all contexts.
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    Examples:   -ptrace FOO.trc #0:#1000
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                -ptrace BAR.trc @2000:
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                -ptrace BLAH.trc :1500
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                -ptrace UXXE.trc :
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                -ptrace FOOBAR.trc @main:+278
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  Branch predictor configuration examples for 2-level predictor:
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    Configurations:   N, M, W, X
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      N   # entries in first level (# of shift register(s))
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      W   width of shift register(s)
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      M   # entries in 2nd level (# of counters, or other FSM)
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      X   (yes-1/no-0) xor history and address for 2nd level index
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    Sample predictors:
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      GAg     : 1, W, 2^W, 0
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      GAp     : 1, W, M (M > 2^W), 0
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      PAg     : N, W, 2^W, 0
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      PAp     : N, W, M (M == 2^(N+W)), 0
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      gshare  : 1, W, 2^W, 1
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  Predictor `comb' combines a bimodal and a 2-level predictor.
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  The cache config parameter <config> has the following format:
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    <name>:<nsets>:<bsize>:<assoc>:<repl>
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    <name>   - name of the cache being defined
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    <nsets>  - number of sets in the cache
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    <bsize>  - block size of the cache
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    <assoc>  - associativity of the cache
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    <repl>   - block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random
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    Examples:   -cache:dl1 dl1:4096:32:1:l
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                -dtlb dtlb:128:4096:32:r
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  Cache levels can be unified by pointing a level of the instruction cache
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  hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache
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  configuration arguments.  Most sensible combinations are supported, e.g.,
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    A unified l2 cache (il2 is pointed at dl2):
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      -cache:il1 il1:128:64:1:l -cache:il2 dl2
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      -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
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    Or, a fully unified cache hierarchy (il1 pointed at dl1):
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      -cache:il1 dl1
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      -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
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sim: ** starting performance simulation **
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warning: syscall: sigvec ignored
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warning: syscall: sigvec ignored
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 init_reg_sets
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sim: ** simulation statistics **
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sim_num_insn                8719943 # total number of instructions committed
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sim_num_refs                3472792 # total number of loads and stores committed
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sim_num_loads               2248866 # total number of loads committed
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sim_num_stores         1223926.0000 # total number of stores committed
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sim_num_branches            1812676 # total number of branches committed
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sim_elapsed_time                 11 # total simulation time in seconds
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sim_inst_rate           792722.0909 # simulation speed (in insts/sec)
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sim_total_insn             10000000 # total number of instructions executed
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sim_total_refs              3951118 # total number of loads and stores executed
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sim_total_loads             2629542 # total number of loads executed
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sim_total_stores       1321576.0000 # total number of stores executed
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sim_total_branches          2093244 # total number of branches executed
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sim_cycle                  10902054 # total simulation time in cycles
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sim_IPC                      0.7998 # instructions per cycle
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sim_CPI                      1.2502 # cycles per instruction
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sim_exec_BW                  0.9173 # total instructions (mis-spec + committed) per cycle
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sim_IPB                      4.8105 # instruction per branch
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IFQ_count                  13738353 # cumulative IFQ occupancy
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IFQ_fcount                  2733952 # cumulative IFQ full count
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ifq_occupancy                1.2602 # avg IFQ occupancy (insn's)
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ifq_rate                     0.9173 # avg IFQ dispatch rate (insn/cycle)
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ifq_latency                  1.3738 # avg IFQ occupant latency (cycle's)
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ifq_full                     0.2508 # fraction of time (cycle's) IFQ was full
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RUU_count                  51435453 # cumulative RUU occupancy
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RUU_fcount                   816180 # cumulative RUU full count
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ruu_occupancy                4.7180 # avg RUU occupancy (insn's)
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ruu_rate                     0.9173 # avg RUU dispatch rate (insn/cycle)
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ruu_latency                  5.1435 # avg RUU occupant latency (cycle's)
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ruu_full                     0.0749 # fraction of time (cycle's) RUU was full
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LSQ_count                  20700795 # cumulative LSQ occupancy
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LSQ_fcount                   716983 # cumulative LSQ full count
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lsq_occupancy                1.8988 # avg LSQ occupancy (insn's)
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lsq_rate                     0.9173 # avg LSQ dispatch rate (insn/cycle)
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lsq_latency                  2.0701 # avg LSQ occupant latency (cycle's)
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lsq_full                     0.0658 # fraction of time (cycle's) LSQ was full
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bpred_bimod.lookups         2179972 # total number of bpred lookups
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bpred_bimod.updates         1812675 # total number of updates
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bpred_bimod.addr_hits       1584928 # total number of address-predicted hits
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bpred_bimod.dir_hits        1633070 # total number of direction-predicted hits (includes addr-hits)
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bpred_bimod.misses           179605 # total number of misses
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bpred_bimod.jr_hits          161143 # total number of address-predicted hits for JR's
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bpred_bimod.jr_seen          198743 # total number of JR's seen
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bpred_bimod.jr_non_ras_hits.PP        22393 # total number of address-predicted hits for non-RAS JR's
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bpred_bimod.jr_non_ras_seen.PP        54322 # total number of non-RAS JR's seen
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bpred_bimod.bpred_addr_rate    0.8744 # branch address-prediction rate (i.e., addr-hits/updates)
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bpred_bimod.bpred_dir_rate    0.9009 # branch direction-prediction rate (i.e., all-hits/updates)
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bpred_bimod.bpred_jr_rate    0.8108 # JR address-prediction rate (i.e., JR addr-hits/JRs seen)
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bpred_bimod.bpred_jr_non_ras_rate.PP    0.4122 # non-RAS JR addr-pred rate (ie, non-RAS JR hits/JRs seen)
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bpred_bimod.retstack_pushes       175081 # total number of address pushed onto ret-addr stack
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bpred_bimod.retstack_pops       165005 # total number of address popped off of ret-addr stack
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bpred_bimod.used_ras.PP       144421 # total number of RAS predictions used
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bpred_bimod.ras_hits.PP       138750 # total number of RAS hits
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bpred_bimod.ras_rate.PP    0.9607 # RAS prediction rate (i.e., RAS hits/used RAS)
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il1.accesses               11367480 # total number of accesses
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il1.hits                   10380169 # total number of hits
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il1.misses                   987311 # total number of misses
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il1.replacements             986799 # total number of replacements
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il1.writebacks                    0 # total number of writebacks
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il1.invalidations                 0 # total number of invalidations
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il1.miss_rate                0.0869 # miss rate (i.e., misses/ref)
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il1.repl_rate                0.0868 # replacement rate (i.e., repls/ref)
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il1.wb_rate                  0.0000 # writeback rate (i.e., wrbks/ref)
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il1.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)
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dl1.accesses                3613728 # total number of accesses
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dl1.hits                    3552399 # total number of hits
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dl1.misses                    61329 # total number of misses
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dl1.replacements              60817 # total number of replacements
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dl1.writebacks                23182 # total number of writebacks
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dl1.invalidations                 0 # total number of invalidations
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dl1.miss_rate                0.0170 # miss rate (i.e., misses/ref)
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dl1.repl_rate                0.0168 # replacement rate (i.e., repls/ref)
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dl1.wb_rate                  0.0064 # writeback rate (i.e., wrbks/ref)
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dl1.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)
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ul2.accesses                1071822 # total number of accesses
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ul2.hits                    1046170 # total number of hits
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ul2.misses                    25652 # total number of misses
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ul2.replacements              21556 # total number of replacements
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ul2.writebacks                 5423 # total number of writebacks
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ul2.invalidations                 0 # total number of invalidations
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ul2.miss_rate                0.0239 # miss rate (i.e., misses/ref)
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ul2.repl_rate                0.0201 # replacement rate (i.e., repls/ref)
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ul2.wb_rate                  0.0051 # writeback rate (i.e., wrbks/ref)
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ul2.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)
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itlb.accesses              11367480 # total number of accesses
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itlb.hits                  11355781 # total number of hits
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itlb.misses                   11699 # total number of misses
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itlb.replacements             11635 # total number of replacements
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itlb.writebacks                   0 # total number of writebacks
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itlb.invalidations                0 # total number of invalidations
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itlb.miss_rate               0.0010 # miss rate (i.e., misses/ref)
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itlb.repl_rate               0.0010 # replacement rate (i.e., repls/ref)
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itlb.wb_rate                 0.0000 # writeback rate (i.e., wrbks/ref)
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itlb.inv_rate                0.0000 # invalidation rate (i.e., invs/ref)
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dtlb.accesses               3646802 # total number of accesses
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dtlb.hits                   3646589 # total number of hits
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dtlb.misses                     213 # total number of misses
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dtlb.replacements                89 # total number of replacements
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dtlb.writebacks                   0 # total number of writebacks
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dtlb.invalidations                0 # total number of invalidations
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dtlb.miss_rate               0.0001 # miss rate (i.e., misses/ref)
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dtlb.repl_rate               0.0000 # replacement rate (i.e., repls/ref)
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dtlb.wb_rate                 0.0000 # writeback rate (i.e., wrbks/ref)
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dtlb.inv_rate                0.0000 # invalidation rate (i.e., invs/ref)
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rename_power            967881.4778 # total power usage of rename unit
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bpred_power            12465654.3537 # total power usage of bpred unit
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window_power           5642207.8086 # total power usage of instruction window
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lsq_power              2199578.3245 # total power usage of load/store queue
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regfile_power          8393593.2278 # total power usage of arch. regfile
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icache_power           7317334.8351 # total power usage of icache
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dcache_power           21754184.8818 # total power usage of dcache
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dcache2_power          13422214.0261 # total power usage of dcache2
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alu_power              53055272.8492 # total power usage of alu
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falu_power             40001991.4249 # total power usage of falu
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resultbus_power        5444402.9746 # total power usage of resultbus
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clock_power            110327937.5607 # total power usage of clock
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avg_rename_power             0.0888 # avg power usage of rename unit
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avg_bpred_power              1.1434 # avg power usage of bpred unit
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avg_window_power             0.5175 # avg power usage of instruction window
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avg_lsq_power                0.2018 # avg power usage of lsq
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avg_regfile_power            0.7699 # avg power usage of arch. regfile
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avg_icache_power             0.6712 # avg power usage of icache
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avg_dcache_power             1.9954 # avg power usage of dcache
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avg_dcache2_power            1.2312 # avg power usage of dcache2
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avg_alu_power                4.8665 # avg power usage of alu
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avg_falu_power               3.6692 # avg power usage of falu
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avg_resultbus_power          0.4994 # avg power usage of resultbus
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avg_clock_power             10.1199 # avg power usage of clock
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fetch_stage_power      19782989.1888 # total power usage of fetch stage
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dispatch_stage_power    967881.4778 # total power usage of dispatch stage
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issue_stage_power      101517860.8647 # total power usage of issue stage
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avg_fetch_power              1.8146 # average power of fetch unit per cycle
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avg_dispatch_power           0.0888 # average power of dispatch unit per cycle
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avg_issue_power              9.3118 # average power of issue unit per cycle
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total_power            240990262.3198 # total power per cycle
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avg_total_power_cycle       22.1050 # average total power per cycle
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avg_total_power_cycle_nofp_nod2      17.2047 # average total power per cycle
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avg_total_power_insn        24.0990 # average total power per insn
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avg_total_power_insn_nofp_nod2      18.7566 # average total power per insn
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rename_power_cc1        312975.6478 # total power usage of rename unit_cc1
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bpred_power_cc1        1772654.8351 # total power usage of bpred unit_cc1
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window_power_cc1       3371208.2019 # total power usage of instruction window_cc1
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lsq_power_cc1           254955.0582 # total power usage of lsq_cc1
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regfile_power_cc1      3726732.5201 # total power usage of arch. regfile_cc1
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icache_power_cc1       2949453.9247 # total power usage of icache_cc1
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dcache_power_cc1       5005768.3915 # total power usage of dcache_cc1
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dcache2_power_cc1      1288371.6533 # total power usage of dcache2_cc1
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alu_power_cc1          5146239.6867 # total power usage of alu_cc1
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resultbus_power_cc1    2238865.7845 # total power usage of resultbus_cc1
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clock_power_cc1        24625365.4139 # total power usage of clock_cc1
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avg_rename_power_cc1         0.0287 # avg power usage of rename unit_cc1
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avg_bpred_power_cc1          0.1626 # avg power usage of bpred unit_cc1
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avg_window_power_cc1         0.3092 # avg power usage of instruction window_cc1
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avg_lsq_power_cc1            0.0234 # avg power usage of lsq_cc1
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avg_regfile_power_cc1        0.3418 # avg power usage of arch. regfile_cc1
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avg_icache_power_cc1         0.2705 # avg power usage of icache_cc1
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avg_dcache_power_cc1         0.4592 # avg power usage of dcache_cc1
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avg_dcache2_power_cc1        0.1182 # avg power usage of dcache2_cc1
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avg_alu_power_cc1            0.4720 # avg power usage of alu_cc1
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avg_resultbus_power_cc1       0.2054 # avg power usage of resultbus_cc1
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avg_clock_power_cc1          2.2588 # avg power usage of clock_cc1
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fetch_stage_power_cc1  4722108.7598 # total power usage of fetch stage_cc1
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dispatch_stage_power_cc1  312975.6478 # total power usage of dispatch stage_cc1
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issue_stage_power_cc1  17305408.7760 # total power usage of issue stage_cc1
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avg_fetch_power_cc1          0.4331 # average power of fetch unit per cycle_cc1
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avg_dispatch_power_cc1       0.0287 # average power of dispatch unit per cycle_cc1
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avg_issue_power_cc1          1.5874 # average power of issue unit per cycle_cc1
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total_power_cycle_cc1  50692591.1175 # total power per cycle_cc1
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avg_total_power_cycle_cc1       4.6498 # average total power per cycle_cc1
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avg_total_power_insn_cc1       5.0693 # average total power per insn_cc1
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rename_power_cc2        221161.7310 # total power usage of rename unit_cc2
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bpred_power_cc2        1036326.7327 # total power usage of bpred unit_cc2
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window_power_cc2       1873345.0308 # total power usage of instruction window_cc2
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lsq_power_cc2           173553.1792 # total power usage of lsq_cc2
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regfile_power_cc2       737402.4659 # total power usage of arch. regfile_cc2
367
icache_power_cc2       2949453.9247 # total power usage of icache_cc2
368
dcache_power_cc2       3605453.9369 # total power usage of dcache_cc2
369
dcache2_power_cc2       659794.2133 # total power usage of dcache2_cc2
370
alu_power_cc2          2699263.2228 # total power usage of alu_cc2
371
resultbus_power_cc2    1192587.7424 # total power usage of resultbus_cc2
372
clock_power_cc2        14570297.5307 # total power usage of clock_cc2
373
avg_rename_power_cc2         0.0203 # avg power usage of rename unit_cc2
374
avg_bpred_power_cc2          0.0951 # avg power usage of bpred unit_cc2
375
avg_window_power_cc2         0.1718 # avg power usage of instruction window_cc2
376
avg_lsq_power_cc2            0.0159 # avg power usage of instruction lsq_cc2
377
avg_regfile_power_cc2        0.0676 # avg power usage of arch. regfile_cc2
378
avg_icache_power_cc2         0.2705 # avg power usage of icache_cc2
379
avg_dcache_power_cc2         0.3307 # avg power usage of dcache_cc2
380
avg_dcache2_power_cc2        0.0605 # avg power usage of dcache2_cc2
381
avg_alu_power_cc2            0.2476 # avg power usage of alu_cc2
382
avg_resultbus_power_cc2       0.1094 # avg power usage of resultbus_cc2
383
avg_clock_power_cc2          1.3365 # avg power usage of clock_cc2
384
fetch_stage_power_cc2  3985780.6573 # total power usage of fetch stage_cc2
385
dispatch_stage_power_cc2  221161.7310 # total power usage of dispatch stage_cc2
386
issue_stage_power_cc2  10203997.3254 # total power usage of issue stage_cc2
387
avg_fetch_power_cc2          0.3656 # average power of fetch unit per cycle_cc2
388
avg_dispatch_power_cc2       0.0203 # average power of dispatch unit per cycle_cc2
389
avg_issue_power_cc2          0.9360 # average power of issue unit per cycle_cc2
390
total_power_cycle_cc2  29718639.7103 # total power per cycle_cc2
391
avg_total_power_cycle_cc2       2.7260 # average total power per cycle_cc2
392
avg_total_power_insn_cc2       2.9719 # average total power per insn_cc2
393
rename_power_cc3        286652.3140 # total power usage of rename unit_cc3
394
bpred_power_cc3        2106951.6818 # total power usage of bpred unit_cc3
395
window_power_cc3       2084963.8708 # total power usage of instruction window_cc3
396
lsq_power_cc3           366697.3026 # total power usage of lsq_cc3
397
regfile_power_cc3      1171221.2043 # total power usage of arch. regfile_cc3
398
icache_power_cc3       3386242.0160 # total power usage of icache_cc3
399
dcache_power_cc3       5291187.7897 # total power usage of dcache_cc3
400
dcache2_power_cc3      1873261.6160 # total power usage of dcache2_cc3
401
alu_power_cc3          7490166.5392 # total power usage of alu_cc3
402
resultbus_power_cc3    1505982.0958 # total power usage of resultbus_cc3
403
clock_power_cc3        23095812.6117 # total power usage of clock_cc3
404
avg_rename_power_cc3         0.0263 # avg power usage of rename unit_cc3
405
avg_bpred_power_cc3          0.1933 # avg power usage of bpred unit_cc3
406
avg_window_power_cc3         0.1912 # avg power usage of instruction window_cc3
407
avg_lsq_power_cc3            0.0336 # avg power usage of instruction lsq_cc3
408
avg_regfile_power_cc3        0.1074 # avg power usage of arch. regfile_cc3
409
avg_icache_power_cc3         0.3106 # avg power usage of icache_cc3
410
avg_dcache_power_cc3         0.4853 # avg power usage of dcache_cc3
411
avg_dcache2_power_cc3        0.1718 # avg power usage of dcache2_cc3
412
avg_alu_power_cc3            0.6870 # avg power usage of alu_cc3
413
avg_resultbus_power_cc3       0.1381 # avg power usage of resultbus_cc3
414
avg_clock_power_cc3          2.1185 # avg power usage of clock_cc3
415
fetch_stage_power_cc3  5493193.6978 # total power usage of fetch stage_cc3
416
dispatch_stage_power_cc3  286652.3140 # total power usage of dispatch stage_cc3
417
issue_stage_power_cc3  18612259.2141 # total power usage of issue stage_cc3
418
avg_fetch_power_cc3          0.5039 # average power of fetch unit per cycle_cc3
419
avg_dispatch_power_cc3       0.0263 # average power of dispatch unit per cycle_cc3
420
avg_issue_power_cc3          1.7072 # average power of issue unit per cycle_cc3
421
total_power_cycle_cc3  48659139.0419 # total power per cycle_cc3
422
avg_total_power_cycle_cc3       4.4633 # average total power per cycle_cc3
423
avg_total_power_insn_cc3       4.8659 # average total power per insn_cc3
424
total_rename_access         9964514 # total number accesses of rename unit
425
total_bpred_access          1812675 # total number accesses of bpred unit
426
total_window_access        36517951 # total number accesses of instruction window
427
total_lsq_access            3703035 # total number accesses of load/store queue
428
total_regfile_access       12733497 # total number accesses of arch. regfile
429
total_icache_access        11409066 # total number accesses of icache
430
total_dcache_access         3613728 # total number accesses of dcache
431
total_dcache2_access        1071822 # total number accesses of dcache2
432
total_alu_access            9017660 # total number accesses of alu
433
total_resultbus_access      9833635 # total number accesses of resultbus
434
avg_rename_access            0.9140 # avg number accesses of rename unit
435
avg_bpred_access             0.1663 # avg number accesses of bpred unit
436
avg_window_access            3.3496 # avg number accesses of instruction window
437
avg_lsq_access               0.3397 # avg number accesses of lsq
438
avg_regfile_access           1.1680 # avg number accesses of arch. regfile
439
avg_icache_access            1.0465 # avg number accesses of icache
440
avg_dcache_access            0.3315 # avg number accesses of dcache
441
avg_dcache2_access           0.0983 # avg number accesses of dcache2
442
avg_alu_access               0.8272 # avg number accesses of alu
443
avg_resultbus_access         0.9020 # avg number accesses of resultbus
444
max_rename_access                 4 # max number accesses of rename unit
445
max_bpred_access                  4 # max number accesses of bpred unit
446
max_window_access                16 # max number accesses of instruction window
447
max_lsq_access                    6 # max number accesses of load/store queue
448
max_regfile_access               12 # max number accesses of arch. regfile
449
max_icache_access                 4 # max number accesses of icache
450
max_dcache_access                 4 # max number accesses of dcache
451
max_dcache2_access                6 # max number accesses of dcache2
452
max_alu_access                    4 # max number accesses of alu
453
max_resultbus_access              8 # max number accesses of resultbus
454
max_cycle_power_cc1         12.0118 # maximum cycle power usage of cc1
455
max_cycle_power_cc2          9.2141 # maximum cycle power usage of cc2
456
max_cycle_power_cc3         10.3187 # maximum cycle power usage of cc3
457
parasitic_power_cc3    8549840.1295 # total parasitic power cc3
458
onchip parasitic_power_cc3 2725513.5000 # onchip parasitic power cc3
459
offchip parasitic_power_cc3 5824326.6295 # offchip parasitic power cc3
460
min amperage                 0.0000 # min amperage
461
max amperage                 5.4309 # max amperage
462
slow_cycles                  0.0000 # slow cycles
463
fast_cycles                  0.0000 # fast cycles
464
sim_invalid_addrs                 0 # total non-speculative bogus addresses seen (debug var)
465
ld_text_base             0x00400000 # program text (code) segment base
466
ld_text_size                2485696 # program text (code) size in bytes
467
ld_data_base             0x10000000 # program initialized data segment base
468
ld_data_size                 287696 # program init'ed `.data' and uninit'ed `.bss' size in bytes
469
ld_stack_base            0x7fffc000 # program stack segment base (highest address in stack)
470
ld_stack_size                 16384 # program initial stack size
471
ld_prog_entry            0x00400140 # program entry point (initial PC)
472
ld_environ_base          0x7fff8000 # program environment base address address
473
ld_target_big_endian              0 # target executable endian-ness, non-zero if big endian
474
mem.page_count                  765 # total number of pages allocated
475
mem.page_mem                  3060k # total size of memory pages allocated
476
mem.ptab_misses                1077 # total first level page table misses
477
mem.ptab_accesses          37143526 # total page table accesses
478
mem.ptab_miss_rate           0.0000 # first level page table miss rate
479

    
480

    
481
Cache Parameters:
482
  Size in bytes: 16384
483
  Number of sets: 512
484
  Associativity: 4
485
  Block Size (bytes): 8
486

    
487
Access Time: 9.27925e-09
488
Cycle Time:  1.09081e-08
489

    
490
Best Ndwl (L1): 8
491
Best Ndbl (L1): 1
492
Best Nspd (L1): 1
493
Best Ntwl (L1): 1
494
Best Ntbl (L1): 4
495
Best Ntspd (L1): 1
496

    
497
Time Components:
498
 data side (with Output driver) (ns): 8.44162
499
 tag side (ns): 8.55667
500
 decode_data (ns): 5.29318
501
 wordline_data (ns): 1.03507
502
 bitline_data (ns): 0.810785
503
 sense_amp_data (ns): 0.58
504
 decode_tag (ns): 2.37065
505
 wordline_tag (ns): 1.36749
506
 bitline_tag (ns): 0.158246
507
 sense_amp_tag (ns): 0.26
508
 compare (ns): 2.42991
509
 mux driver (ns): 1.6125
510
 sel inverter (ns): 0.357877
511
 data output driver (ns): 0.722579
512
 total data path (with output driver) (ns): 7.71904
513
 total tag path is set assoc (ns): 8.55667
514
 precharge time (ns): 1.6289
515

    
516
Cache Parameters:
517
  Size in bytes: 16384
518
  Number of sets: 512
519
  Associativity: 1
520
  Block Size (bytes): 32
521

    
522
Access Time: 6.07496e-09
523
Cycle Time:  7.99836e-09
524

    
525
Best Ndwl (L1): 2
526
Best Ndbl (L1): 2
527
Best Nspd (L1): 1
528
Best Ntwl (L1): 1
529
Best Ntbl (L1): 2
530
Best Ntspd (L1): 2
531

    
532
Time Components:
533
 data side (with Output driver) (ns): 6.07496
534
 tag side (ns): 6.05737
535
 decode_data (ns): 2.92313
536
 wordline_data (ns): 1.32956
537
 bitline_data (ns): 0.452976
538
 sense_amp_data (ns): 0.58
539
 decode_tag (ns): 1.84499
540
 wordline_tag (ns): 0.825016
541
 bitline_tag (ns): 0.252886
542
 sense_amp_tag (ns): 0.26
543
 compare (ns): 2.30022
544
 valid signal driver (ns): 0.574251
545
 data output driver (ns): 0.789293
546
 total data path (with output driver) (ns): 5.28567
547
 total tag path is dm (ns): 6.05737
548
 precharge time (ns): 1.92339
549

    
550
Cache Parameters:
551
  Size in bytes: 16384
552
  Number of sets: 128
553
  Associativity: 4
554
  Block Size (bytes): 32
555

    
556
Access Time: 9.14093e-09
557
Cycle Time:  1.11718e-08
558

    
559
Best Ndwl (L1): 4
560
Best Ndbl (L1): 2
561
Best Nspd (L1): 1
562
Best Ntwl (L1): 1
563
Best Ntbl (L1): 2
564
Best Ntspd (L1): 1
565

    
566
Time Components:
567
 data side (with Output driver) (ns): 6.05114
568
 tag side (ns): 7.98848
569
 decode_data (ns): 2.92572
570
 wordline_data (ns): 1.437
571
 bitline_data (ns): -0.0440331
572
 sense_amp_data (ns): 0.58
573
 decode_tag (ns): 1.46851
574
 wordline_tag (ns): 1.27791
575
 bitline_tag (ns): -0.0315811
576
 sense_amp_tag (ns): 0.26
577
 compare (ns): 2.29478
578
 mux driver (ns): 2.37376
579
 sel inverter (ns): 0.345094
580
 data output driver (ns): 1.15245
581
 total data path (with output driver) (ns): 4.89869
582
 total tag path is set assoc (ns): 7.98848
583
 precharge time (ns): 2.03083
584

    
585
Cache Parameters:
586
  Size in bytes: 262144
587
  Number of sets: 1024
588
  Associativity: 4
589
  Block Size (bytes): 64
590

    
591
Access Time: 1.44948e-08
592
Cycle Time:  1.76863e-08
593

    
594
Best Ndwl (L1): 2
595
Best Ndbl (L1): 2
596
Best Nspd (L1): 1
597
Best Ntwl (L1): 1
598
Best Ntbl (L1): 4
599
Best Ntspd (L1): 1
600

    
601
Time Components:
602
 data side (with Output driver) (ns): 11.3269
603
 tag side (ns): 12.2049
604
 decode_data (ns): 4.99158
605
 wordline_data (ns): 2.59771
606
 bitline_data (ns): 0.867749
607
 sense_amp_data (ns): 0.58
608
 decode_tag (ns): 4.52586
609
 wordline_tag (ns): 1.24192
610
 bitline_tag (ns): 0.46158
611
 sense_amp_tag (ns): 0.26
612
 compare (ns): 2.17054
613
 mux driver (ns): 3.21212
614
 sel inverter (ns): 0.332908
615
 data output driver (ns): 2.28987
616
 total data path (with output driver) (ns): 9.03704
617
 total tag path is set assoc (ns): 12.2049
618
 precharge time (ns): 3.19154