Revision 60 spec/gzip/gzip_orig.txt

View differences:

gzip_orig.txt
62 62
 bitline_power (W): 0.83087
63 63
 senseamp_power (W): 0.14592
64 64
 tagarray_power (W): 0.147353
65
sim: command line: ./sim-outorder gzip00.O2unroll.gcc.100M.ss input.source 
65
sim: command line: ./sim-outorder -max:inst 70000000 gzip00.O2unroll.gcc.100M.ss input.source 
66 66

  
67
sim: simulation started @ Mon Nov 30 11:23:44 2009, options follow:
67
sim: simulation started @ Tue Dec  1 19:12:51 2009, options follow:
68 68

  
69 69
sim-outorder: This simulator implements a very detailed out-of-order issue
70 70
superscalar processor with a two-level memory system and speculative
......
83 83
# -redir:sim           <null> # redirect simulator output to file (non-interactive only)
84 84
# -redir:prog          <null> # redirect simulated program output to file
85 85
-nice                       0 # simulator scheduling priority
86
-max:inst                   0 # maximum number of inst's to execute
86
-max:inst            70000000 # maximum number of inst's to execute
87 87
-fastfwd                    0 # number of insts skipped before timing starts
88 88
# -ptrace              <null> # generate pipetrace, i.e., <fname|stdout|stderr> <range>
89 89
-fetch:ifqsize              4 # instruction fetch queue size (in insts)
......
186 186

  
187 187

  
188 188
sim: ** starting performance simulation **
189
spec_init
190
Loading Input Data
191
Duplicating 9553920 bytes
192
Duplicating 19107840 bytes
193
Duplicating 28893184 bytes
194
Input data 67108864 bytes in length
195
Compressing Input Data, level 1
196
Compressed data 21267049 bytes in length
197
Uncompressing Data
198
Uncompressed data 67108864 bytes in length
199
Uncompressed data compared correctly
200
Compressing Input Data, level 3
201
Compressed data 19456545 bytes in length
202
Uncompressing Data
203
Uncompressed data 67108864 bytes in length
204
Uncompressed data compared correctly
205
Compressing Input Data, level 5
206
Compressed data 17614334 bytes in length
207
Uncompressing Data
208
Uncompressed data 67108864 bytes in length
209
Uncompressed data compared correctly
210
Compressing Input Data, level 7
211
Compressed data 17251180 bytes in length
212
Uncompressing Data
213
Uncompressed data 67108864 bytes in length
214
Uncompressed data compared correctly
215
Compressing Input Data, level 9
216
Compressed data 17212050 bytes in length
217
Uncompressing Data
218
Uncompressed data 67108864 bytes in length
219
Uncompressed data compared correctly
220
Tested 64MB buffer: OK!
221 189

  
222 190
sim: ** simulation statistics **
223
sim_num_insn            64370451696 # total number of instructions committed
224
sim_num_refs            17416903471 # total number of loads and stores committed
225
sim_num_loads           13125894168 # total number of loads committed
226
sim_num_stores         4291009303.0000 # total number of stores committed
227
sim_num_branches        12031113652 # total number of branches committed
228
sim_elapsed_time              60670 # total simulation time in seconds
229
sim_inst_rate          1060993.1053 # simulation speed (in insts/sec)
230
sim_total_insn          72569295080 # total number of instructions executed
231
sim_total_refs          19761348855 # total number of loads and stores executed
232
sim_total_loads         14962903089 # total number of loads executed
233
sim_total_stores       4798445766.0000 # total number of stores executed
234
sim_total_branches      13596051264 # total number of branches executed
235
sim_cycle               42212101867 # total simulation time in cycles
236
sim_IPC                      1.5249 # instructions per cycle
237
sim_CPI                      0.6558 # cycles per instruction
238
sim_exec_BW                  1.7192 # total instructions (mis-spec + committed) per cycle
239
sim_IPB                      5.3503 # instruction per branch
240
IFQ_count              147570074716 # cumulative IFQ occupancy
241
IFQ_fcount              34470031331 # cumulative IFQ full count
242
ifq_occupancy                3.4959 # avg IFQ occupancy (insn's)
243
ifq_rate                     1.7192 # avg IFQ dispatch rate (insn/cycle)
244
ifq_latency                  2.0335 # avg IFQ occupant latency (cycle's)
245
ifq_full                     0.8166 # fraction of time (cycle's) IFQ was full
246
RUU_count              584966513777 # cumulative RUU occupancy
247
RUU_fcount              27586361216 # cumulative RUU full count
248
ruu_occupancy               13.8578 # avg RUU occupancy (insn's)
249
ruu_rate                     1.7192 # avg RUU dispatch rate (insn/cycle)
250
ruu_latency                  8.0608 # avg RUU occupant latency (cycle's)
251
ruu_full                     0.6535 # fraction of time (cycle's) RUU was full
252
LSQ_count              157161096198 # cumulative LSQ occupancy
253
LSQ_fcount               3117301718 # cumulative LSQ full count
254
lsq_occupancy                3.7231 # avg LSQ occupancy (insn's)
255
lsq_rate                     1.7192 # avg LSQ dispatch rate (insn/cycle)
256
lsq_latency                  2.1657 # avg LSQ occupant latency (cycle's)
257
lsq_full                     0.0738 # fraction of time (cycle's) LSQ was full
258
bpred_bimod.lookups     14148051604 # total number of bpred lookups
259
bpred_bimod.updates     12031113652 # total number of updates
260
bpred_bimod.addr_hits   11262876015 # total number of address-predicted hits
261
bpred_bimod.dir_hits    11267091760 # total number of direction-predicted hits (includes addr-hits)
262
bpred_bimod.misses        764021892 # total number of misses
263
bpred_bimod.jr_hits       266070508 # total number of address-predicted hits for JR's
264
bpred_bimod.jr_seen       270318863 # total number of JR's seen
265
bpred_bimod.jr_non_ras_hits.PP       223687 # total number of address-predicted hits for non-RAS JR's
266
bpred_bimod.jr_non_ras_seen.PP      1027630 # total number of non-RAS JR's seen
267
bpred_bimod.bpred_addr_rate    0.9361 # branch address-prediction rate (i.e., addr-hits/updates)
268
bpred_bimod.bpred_dir_rate    0.9365 # branch direction-prediction rate (i.e., all-hits/updates)
269
bpred_bimod.bpred_jr_rate    0.9843 # JR address-prediction rate (i.e., JR addr-hits/JRs seen)
270
bpred_bimod.bpred_jr_non_ras_rate.PP    0.2177 # non-RAS JR addr-pred rate (ie, non-RAS JR hits/JRs seen)
271
bpred_bimod.retstack_pushes    351039727 # total number of address pushed onto ret-addr stack
272
bpred_bimod.retstack_pops    326647030 # total number of address popped off of ret-addr stack
273
bpred_bimod.used_ras.PP    269291233 # total number of RAS predictions used
274
bpred_bimod.ras_hits.PP    265846821 # total number of RAS hits
275
bpred_bimod.ras_rate.PP    0.9872 # RAS prediction rate (i.e., RAS hits/used RAS)
276
il1.accesses            75366103087 # total number of accesses
277
il1.hits                75335279379 # total number of hits
278
il1.misses                 30823708 # total number of misses
279
il1.replacements           30823196 # total number of replacements
191
sim_num_insn               64710066 # total number of instructions committed
192
sim_num_refs               38510221 # total number of loads and stores committed
193
sim_num_loads              20847548 # total number of loads committed
194
sim_num_stores         17662673.0000 # total number of stores committed
195
sim_num_branches            5975255 # total number of branches committed
196
sim_elapsed_time                 74 # total simulation time in seconds
197
sim_inst_rate           874460.3514 # simulation speed (in insts/sec)
198
sim_total_insn             70000001 # total number of instructions executed
199
sim_total_refs             40273921 # total number of loads and stores executed
200
sim_total_loads            22181581 # total number of loads executed
201
sim_total_stores       18092340.0000 # total number of stores executed
202
sim_total_branches          6914514 # total number of branches executed
203
sim_cycle                  65817968 # total simulation time in cycles
204
sim_IPC                      0.9832 # instructions per cycle
205
sim_CPI                      1.0171 # cycles per instruction
206
sim_exec_BW                  1.0635 # total instructions (mis-spec + committed) per cycle
207
sim_IPB                     10.8297 # instruction per branch
208
IFQ_count                 253321064 # cumulative IFQ occupancy
209
IFQ_fcount                 62003184 # cumulative IFQ full count
210
ifq_occupancy                3.8488 # avg IFQ occupancy (insn's)
211
ifq_rate                     1.0635 # avg IFQ dispatch rate (insn/cycle)
212
ifq_latency                  3.6189 # avg IFQ occupant latency (cycle's)
213
ifq_full                     0.9420 # fraction of time (cycle's) IFQ was full
214
RUU_count                 646922030 # cumulative RUU occupancy
215
RUU_fcount                 12020877 # cumulative RUU full count
216
ruu_occupancy                9.8290 # avg RUU occupancy (insn's)
217
ruu_rate                     1.0635 # avg RUU dispatch rate (insn/cycle)
218
ruu_latency                  9.2417 # avg RUU occupant latency (cycle's)
219
ruu_full                     0.1826 # fraction of time (cycle's) RUU was full
220
LSQ_count                 455547948 # cumulative LSQ occupancy
221
LSQ_fcount                 44794673 # cumulative LSQ full count
222
lsq_occupancy                6.9213 # avg LSQ occupancy (insn's)
223
lsq_rate                     1.0635 # avg LSQ dispatch rate (insn/cycle)
224
lsq_latency                  6.5078 # avg LSQ occupant latency (cycle's)
225
lsq_full                     0.6806 # fraction of time (cycle's) LSQ was full
226
bpred_bimod.lookups         7261816 # total number of bpred lookups
227
bpred_bimod.updates         5975253 # total number of updates
228
bpred_bimod.addr_hits       5461545 # total number of address-predicted hits
229
bpred_bimod.dir_hits        5467181 # total number of direction-predicted hits (includes addr-hits)
230
bpred_bimod.misses           508072 # total number of misses
231
bpred_bimod.jr_hits          212639 # total number of address-predicted hits for JR's
232
bpred_bimod.jr_seen          217936 # total number of JR's seen
233
bpred_bimod.jr_non_ras_hits.PP           18 # total number of address-predicted hits for non-RAS JR's
234
bpred_bimod.jr_non_ras_seen.PP           24 # total number of non-RAS JR's seen
235
bpred_bimod.bpred_addr_rate    0.9140 # branch address-prediction rate (i.e., addr-hits/updates)
236
bpred_bimod.bpred_dir_rate    0.9150 # branch direction-prediction rate (i.e., all-hits/updates)
237
bpred_bimod.bpred_jr_rate    0.9757 # JR address-prediction rate (i.e., JR addr-hits/JRs seen)
238
bpred_bimod.bpred_jr_non_ras_rate.PP    0.7500 # non-RAS JR addr-pred rate (ie, non-RAS JR hits/JRs seen)
239
bpred_bimod.retstack_pushes       274861 # total number of address pushed onto ret-addr stack
240
bpred_bimod.retstack_pops       268411 # total number of address popped off of ret-addr stack
241
bpred_bimod.used_ras.PP       217912 # total number of RAS predictions used
242
bpred_bimod.ras_hits.PP       212621 # total number of RAS hits
243
bpred_bimod.ras_rate.PP    0.9757 # RAS prediction rate (i.e., RAS hits/used RAS)
244
il1.accesses               71933391 # total number of accesses
245
il1.hits                   71931029 # total number of hits
246
il1.misses                     2362 # total number of misses
247
il1.replacements               1874 # total number of replacements
280 248
il1.writebacks                    0 # total number of writebacks
281 249
il1.invalidations                 0 # total number of invalidations
282
il1.miss_rate                0.0004 # miss rate (i.e., misses/ref)
283
il1.repl_rate                0.0004 # replacement rate (i.e., repls/ref)
250
il1.miss_rate                0.0000 # miss rate (i.e., misses/ref)
251
il1.repl_rate                0.0000 # replacement rate (i.e., repls/ref)
284 252
il1.wb_rate                  0.0000 # writeback rate (i.e., wrbks/ref)
285 253
il1.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)
286
dl1.accesses            17702251238 # total number of accesses
287
dl1.hits                15204413658 # total number of hits
288
dl1.misses               2497837580 # total number of misses
289
dl1.replacements         2497837068 # total number of replacements
290
dl1.writebacks            329872927 # total number of writebacks
254
dl1.accesses               38966370 # total number of accesses
255
dl1.hits                   34698844 # total number of hits
256
dl1.misses                  4267526 # total number of misses
257
dl1.replacements            4267014 # total number of replacements
258
dl1.writebacks              2204762 # total number of writebacks
291 259
dl1.invalidations                 0 # total number of invalidations
292
dl1.miss_rate                0.1411 # miss rate (i.e., misses/ref)
293
dl1.repl_rate                0.1411 # replacement rate (i.e., repls/ref)
294
dl1.wb_rate                  0.0186 # writeback rate (i.e., wrbks/ref)
260
dl1.miss_rate                0.1095 # miss rate (i.e., misses/ref)
261
dl1.repl_rate                0.1095 # replacement rate (i.e., repls/ref)
262
dl1.wb_rate                  0.0566 # writeback rate (i.e., wrbks/ref)
295 263
dl1.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)
296
ul2.accesses             2858534215 # total number of accesses
297
ul2.hits                 2826262238 # total number of hits
298
ul2.misses                 32271977 # total number of misses
299
ul2.replacements           32267881 # total number of replacements
300
ul2.writebacks             21507246 # total number of writebacks
264
ul2.accesses                6474650 # total number of accesses
265
ul2.hits                    4368543 # total number of hits
266
ul2.misses                  2106107 # total number of misses
267
ul2.replacements            2102011 # total number of replacements
268
ul2.writebacks              1123401 # total number of writebacks
301 269
ul2.invalidations                 0 # total number of invalidations
302
ul2.miss_rate                0.0113 # miss rate (i.e., misses/ref)
303
ul2.repl_rate                0.0113 # replacement rate (i.e., repls/ref)
304
ul2.wb_rate                  0.0075 # writeback rate (i.e., wrbks/ref)
270
ul2.miss_rate                0.3253 # miss rate (i.e., misses/ref)
271
ul2.repl_rate                0.3247 # replacement rate (i.e., repls/ref)
272
ul2.wb_rate                  0.1735 # writeback rate (i.e., wrbks/ref)
305 273
ul2.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)
306
itlb.accesses           75366103087 # total number of accesses
307
itlb.hits               75366103047 # total number of hits
308
itlb.misses                      40 # total number of misses
274
itlb.accesses              71933391 # total number of accesses
275
itlb.hits                  71933363 # total number of hits
276
itlb.misses                      28 # total number of misses
309 277
itlb.replacements                 0 # total number of replacements
310 278
itlb.writebacks                   0 # total number of writebacks
311 279
itlb.invalidations                0 # total number of invalidations
......
313 281
itlb.repl_rate               0.0000 # replacement rate (i.e., repls/ref)
314 282
itlb.wb_rate                 0.0000 # writeback rate (i.e., wrbks/ref)
315 283
itlb.inv_rate                0.0000 # invalidation rate (i.e., invs/ref)
316
dtlb.accesses           18112737968 # total number of accesses
317
dtlb.hits               18112231998 # total number of hits
318
dtlb.misses                  505970 # total number of misses
319
dtlb.replacements            505842 # total number of replacements
284
dtlb.accesses              39016320 # total number of accesses
285
dtlb.hits                  38922031 # total number of hits
286
dtlb.misses                   94289 # total number of misses
287
dtlb.replacements             94161 # total number of replacements
320 288
dtlb.writebacks                   0 # total number of writebacks
321 289
dtlb.invalidations                0 # total number of invalidations
322
dtlb.miss_rate               0.0000 # miss rate (i.e., misses/ref)
323
dtlb.repl_rate               0.0000 # replacement rate (i.e., repls/ref)
290
dtlb.miss_rate               0.0024 # miss rate (i.e., misses/ref)
291
dtlb.repl_rate               0.0024 # replacement rate (i.e., repls/ref)
324 292
dtlb.wb_rate                 0.0000 # writeback rate (i.e., wrbks/ref)
325 293
dtlb.inv_rate                0.0000 # invalidation rate (i.e., invs/ref)
326
rename_power           3747581864.9569 # total power usage of rename unit
327
bpred_power            48266280687.2328 # total power usage of bpred unit
328
window_power           21846289307.4522 # total power usage of instruction window
329
lsq_power              8516642958.0262 # total power usage of load/store queue
330
regfile_power          32499475754.2160 # total power usage of arch. regfile
331
icache_power           28332273525.6432 # total power usage of icache
332
dcache_power           84230956463.0284 # total power usage of dcache
333
dcache2_power          51969985281.0791 # total power usage of dcache2
334
alu_power              205427054474.2720 # total power usage of alu
335
falu_power             154885379974.6880 # total power usage of falu
336
resultbus_power        21080398281.4192 # total power usage of resultbus
337
clock_power            427183493471.9036 # total power usage of clock
294
rename_power           5843301.8391 # total power usage of rename unit
295
bpred_power            75257748.5145 # total power usage of bpred unit
296
window_power           34063182.3109 # total power usage of instruction window
297
lsq_power              13279311.9439 # total power usage of load/store queue
298
regfile_power          50673868.4830 # total power usage of arch. regfile
299
icache_power           44176272.7190 # total power usage of icache
300
dcache_power           131334539.5692 # total power usage of dcache
301
dcache2_power          81032698.4945 # total power usage of dcache2
302
alu_power              320305719.7240 # total power usage of alu
303
falu_power             241500343.8041 # total power usage of falu
304
resultbus_power        32868993.3537 # total power usage of resultbus
305
clock_power            666072712.1809 # total power usage of clock
338 306
avg_rename_power             0.0888 # avg power usage of rename unit
339 307
avg_bpred_power              1.1434 # avg power usage of bpred unit
340 308
avg_window_power             0.5175 # avg power usage of instruction window
......
347 315
avg_falu_power               3.6692 # avg power usage of falu
348 316
avg_resultbus_power          0.4994 # avg power usage of resultbus
349 317
avg_clock_power             10.1199 # avg power usage of clock
350
fetch_stage_power      76598554212.8761 # total power usage of fetch stage
351
dispatch_stage_power   3747581864.9569 # total power usage of dispatch stage
352
issue_stage_power      393071326765.2771 # total power usage of issue stage
318
fetch_stage_power      119434021.2335 # total power usage of fetch stage
319
dispatch_stage_power   5843301.8391 # total power usage of dispatch stage
320
issue_stage_power      612884445.3962 # total power usage of issue stage
353 321
avg_fetch_power              1.8146 # average power of fetch unit per cycle
354 322
avg_dispatch_power           0.0888 # average power of dispatch unit per cycle
355 323
avg_issue_power              9.3118 # average power of issue unit per cycle
356
total_power            933100432069.2296 # total power per cycle
324
total_power            1454908349.1326 # total power per cycle
357 325
avg_total_power_cycle       22.1050 # average total power per cycle
358 326
avg_total_power_cycle_nofp_nod2      17.2047 # average total power per cycle
359
avg_total_power_insn        12.8581 # average total power per insn
360
avg_total_power_insn_nofp_nod2      10.0076 # average total power per insn
361
rename_power_cc1       2555577588.4209 # total power usage of rename unit_cc1
362
bpred_power_cc1        10726234733.7591 # total power usage of bpred unit_cc1
363
window_power_cc1       17496205670.1672 # total power usage of instruction window_cc1
364
lsq_power_cc1          1571667187.9823 # total power usage of lsq_cc1
365
regfile_power_cc1      21095786561.1663 # total power usage of arch. regfile_cc1
366
icache_power_cc1       20115731464.6774 # total power usage of icache_cc1
367
dcache_power_cc1       27203043572.5188 # total power usage of dcache_cc1
368
dcache2_power_cc1      3108503858.2429 # total power usage of dcache2_cc1
369
alu_power_cc1          36044331258.9081 # total power usage of alu_cc1
370
resultbus_power_cc1    14947675709.3777 # total power usage of resultbus_cc1
371
clock_power_cc1        148760466508.3615 # total power usage of clock_cc1
372
avg_rename_power_cc1         0.0605 # avg power usage of rename unit_cc1
373
avg_bpred_power_cc1          0.2541 # avg power usage of bpred unit_cc1
374
avg_window_power_cc1         0.4145 # avg power usage of instruction window_cc1
375
avg_lsq_power_cc1            0.0372 # avg power usage of lsq_cc1
376
avg_regfile_power_cc1        0.4998 # avg power usage of arch. regfile_cc1
377
avg_icache_power_cc1         0.4765 # avg power usage of icache_cc1
378
avg_dcache_power_cc1         0.6444 # avg power usage of dcache_cc1
379
avg_dcache2_power_cc1        0.0736 # avg power usage of dcache2_cc1
380
avg_alu_power_cc1            0.8539 # avg power usage of alu_cc1
381
avg_resultbus_power_cc1       0.3541 # avg power usage of resultbus_cc1
382
avg_clock_power_cc1          3.5241 # avg power usage of clock_cc1
383
fetch_stage_power_cc1  30841966198.4365 # total power usage of fetch stage_cc1
384
dispatch_stage_power_cc1 2555577588.4209 # total power usage of dispatch stage_cc1
385
issue_stage_power_cc1  100371427257.1969 # total power usage of issue stage_cc1
386
avg_fetch_power_cc1          0.7306 # average power of fetch unit per cycle_cc1
387
avg_dispatch_power_cc1       0.0605 # average power of dispatch unit per cycle_cc1
388
avg_issue_power_cc1          2.3778 # average power of issue unit per cycle_cc1
389
total_power_cycle_cc1  303625224113.5820 # total power per cycle_cc1
390
avg_total_power_cycle_cc1       7.1928 # average total power per cycle_cc1
391
avg_total_power_insn_cc1       4.1839 # average total power per insn_cc1
392
rename_power_cc2       1610670335.3298 # total power usage of rename unit_cc2
393
bpred_power_cc2        6878323072.6706 # total power usage of bpred unit_cc2
394
window_power_cc2       12518418350.3719 # total power usage of instruction window_cc2
395
lsq_power_cc2          936829145.4849 # total power usage of lsq_cc2
396
regfile_power_cc2      5202178542.1852 # total power usage of arch. regfile_cc2
397
icache_power_cc2       20115731464.6774 # total power usage of icache_cc2
398
dcache_power_cc2       17661723339.1864 # total power usage of dcache_cc2
399
dcache2_power_cc2      1759661965.5346 # total power usage of dcache2_cc2
400
alu_power_cc2          20056551056.4588 # total power usage of alu_cc2
401
resultbus_power_cc2    8016129108.0042 # total power usage of resultbus_cc2
402
clock_power_cc2        92200037544.4514 # total power usage of clock_cc2
403
avg_rename_power_cc2         0.0382 # avg power usage of rename unit_cc2
404
avg_bpred_power_cc2          0.1629 # avg power usage of bpred unit_cc2
405
avg_window_power_cc2         0.2966 # avg power usage of instruction window_cc2
406
avg_lsq_power_cc2            0.0222 # avg power usage of instruction lsq_cc2
407
avg_regfile_power_cc2        0.1232 # avg power usage of arch. regfile_cc2
408
avg_icache_power_cc2         0.4765 # avg power usage of icache_cc2
409
avg_dcache_power_cc2         0.4184 # avg power usage of dcache_cc2
410
avg_dcache2_power_cc2        0.0417 # avg power usage of dcache2_cc2
411
avg_alu_power_cc2            0.4751 # avg power usage of alu_cc2
412
avg_resultbus_power_cc2       0.1899 # avg power usage of resultbus_cc2
413
avg_clock_power_cc2          2.1842 # avg power usage of clock_cc2
414
fetch_stage_power_cc2  26994054537.3480 # total power usage of fetch stage_cc2
415
dispatch_stage_power_cc2 1610670335.3298 # total power usage of dispatch stage_cc2
416
issue_stage_power_cc2  60949312965.0408 # total power usage of issue stage_cc2
417
avg_fetch_power_cc2          0.6395 # average power of fetch unit per cycle_cc2
418
avg_dispatch_power_cc2       0.0382 # average power of dispatch unit per cycle_cc2
419
avg_issue_power_cc2          1.4439 # average power of issue unit per cycle_cc2
420
total_power_cycle_cc2  186956253924.3553 # total power per cycle_cc2
421
avg_total_power_cycle_cc2       4.4290 # average total power per cycle_cc2
422
avg_total_power_insn_cc2       2.5762 # average total power per insn_cc2
423
rename_power_cc3       1729870680.2731 # total power usage of rename unit_cc3
424
bpred_power_cc3        10634654050.0306 # total power usage of bpred unit_cc3
425
window_power_cc3       12881049037.6976 # total power usage of instruction window_cc3
426
lsq_power_cc3          1627907502.5492 # total power usage of lsq_cc3
427
regfile_power_cc3      6125962463.7474 # total power usage of arch. regfile_cc3
428
icache_power_cc3       20937391089.9910 # total power usage of icache_cc3
429
dcache_power_cc3       23406031296.0216 # total power usage of dcache_cc3
430
dcache2_power_cc3      6645868144.0521 # total power usage of dcache2_cc3
431
alu_power_cc3          36994785967.9134 # total power usage of alu_cc3
432
resultbus_power_cc3    8518378768.7922 # total power usage of resultbus_cc3
433
clock_power_cc3        119711984296.8746 # total power usage of clock_cc3
434
avg_rename_power_cc3         0.0410 # avg power usage of rename unit_cc3
435
avg_bpred_power_cc3          0.2519 # avg power usage of bpred unit_cc3
436
avg_window_power_cc3         0.3052 # avg power usage of instruction window_cc3
437
avg_lsq_power_cc3            0.0386 # avg power usage of instruction lsq_cc3
438
avg_regfile_power_cc3        0.1451 # avg power usage of arch. regfile_cc3
439
avg_icache_power_cc3         0.4960 # avg power usage of icache_cc3
440
avg_dcache_power_cc3         0.5545 # avg power usage of dcache_cc3
441
avg_dcache2_power_cc3        0.1574 # avg power usage of dcache2_cc3
442
avg_alu_power_cc3            0.8764 # avg power usage of alu_cc3
443
avg_resultbus_power_cc3       0.2018 # avg power usage of resultbus_cc3
444
avg_clock_power_cc3          2.8360 # avg power usage of clock_cc3
445
fetch_stage_power_cc3  31572045140.0216 # total power usage of fetch stage_cc3
446
dispatch_stage_power_cc3 1729870680.2731 # total power usage of dispatch stage_cc3
447
issue_stage_power_cc3  90074020717.0261 # total power usage of issue stage_cc3
448
avg_fetch_power_cc3          0.7479 # average power of fetch unit per cycle_cc3
449
avg_dispatch_power_cc3       0.0410 # average power of dispatch unit per cycle_cc3
450
avg_issue_power_cc3          2.1338 # average power of issue unit per cycle_cc3
451
total_power_cycle_cc3  249213883297.9427 # total power per cycle_cc3
452
avg_total_power_cycle_cc3       5.9038 # average total power per cycle_cc3
453
avg_total_power_insn_cc3       3.4342 # average total power per insn_cc3
454
total_rename_access     72569293621 # total number accesses of rename unit
455
total_bpred_access      12031113652 # total number accesses of bpred unit
456
total_window_access    239973583552 # total number accesses of instruction window
457
total_lsq_access        18696519032 # total number accesses of load/store queue
458
total_regfile_access    88808753581 # total number accesses of arch. regfile
459
total_icache_access     75366104710 # total number accesses of icache
460
total_dcache_access     17702251238 # total number accesses of dcache
461
total_dcache2_access     2858534215 # total number accesses of dcache2
462
total_alu_access        67004619708 # total number accesses of alu
463
total_resultbus_access  68994912966 # total number accesses of resultbus
464
avg_rename_access            1.7192 # avg number accesses of rename unit
465
avg_bpred_access             0.2850 # avg number accesses of bpred unit
466
avg_window_access            5.6849 # avg number accesses of instruction window
467
avg_lsq_access               0.4429 # avg number accesses of lsq
468
avg_regfile_access           2.1039 # avg number accesses of arch. regfile
469
avg_icache_access            1.7854 # avg number accesses of icache
470
avg_dcache_access            0.4194 # avg number accesses of dcache
471
avg_dcache2_access           0.0677 # avg number accesses of dcache2
472
avg_alu_access               1.5873 # avg number accesses of alu
473
avg_resultbus_access         1.6345 # avg number accesses of resultbus
327
avg_total_power_insn        20.7844 # average total power per insn
328
avg_total_power_insn_nofp_nod2      16.1768 # average total power per insn
329
rename_power_cc1       2277986.2877 # total power usage of rename unit_cc1
330
bpred_power_cc1        6223923.3440 # total power usage of bpred unit_cc1
331
window_power_cc1       17990562.4965 # total power usage of instruction window_cc1
332
lsq_power_cc1          3057384.7068 # total power usage of lsq_cc1
333
regfile_power_cc1      17955831.7014 # total power usage of arch. regfile_cc1
334
icache_power_cc1       17635672.2228 # total power usage of icache_cc1
335
dcache_power_cc1       50828312.4302 # total power usage of dcache_cc1
336
dcache2_power_cc1      5256143.5116 # total power usage of dcache2_cc1
337
alu_power_cc1          33883207.6635 # total power usage of alu_cc1
338
resultbus_power_cc1    14975922.6938 # total power usage of resultbus_cc1
339
clock_power_cc1        138514635.5836 # total power usage of clock_cc1
340
avg_rename_power_cc1         0.0346 # avg power usage of rename unit_cc1
341
avg_bpred_power_cc1          0.0946 # avg power usage of bpred unit_cc1
342
avg_window_power_cc1         0.2733 # avg power usage of instruction window_cc1
343
avg_lsq_power_cc1            0.0465 # avg power usage of lsq_cc1
344
avg_regfile_power_cc1        0.2728 # avg power usage of arch. regfile_cc1
345
avg_icache_power_cc1         0.2679 # avg power usage of icache_cc1
346
avg_dcache_power_cc1         0.7723 # avg power usage of dcache_cc1
347
avg_dcache2_power_cc1        0.0799 # avg power usage of dcache2_cc1
348
avg_alu_power_cc1            0.5148 # avg power usage of alu_cc1
349
avg_resultbus_power_cc1       0.2275 # avg power usage of resultbus_cc1
350
avg_clock_power_cc1          2.1045 # avg power usage of clock_cc1
351
fetch_stage_power_cc1  23859595.5668 # total power usage of fetch stage_cc1
352
dispatch_stage_power_cc1 2277986.2877 # total power usage of dispatch stage_cc1
353
issue_stage_power_cc1  125991533.5024 # total power usage of issue stage_cc1
354
avg_fetch_power_cc1          0.3625 # average power of fetch unit per cycle_cc1
355
avg_dispatch_power_cc1       0.0346 # average power of dispatch unit per cycle_cc1
356
avg_issue_power_cc1          1.9142 # average power of issue unit per cycle_cc1
357
total_power_cycle_cc1  308599582.6419 # total power per cycle_cc1
358
avg_total_power_cycle_cc1       4.6887 # average total power per cycle_cc1
359
avg_total_power_insn_cc1       4.4086 # average total power per insn_cc1
360
rename_power_cc2       1553634.6847 # total power usage of rename unit_cc2
361
bpred_power_cc2        3416119.5017 # total power usage of bpred unit_cc2
362
window_power_cc2       14105569.5112 # total power usage of instruction window_cc2
363
lsq_power_cc2          1816657.2644 # total power usage of lsq_cc2
364
regfile_power_cc2      6042301.3225 # total power usage of arch. regfile_cc2
365
icache_power_cc2       17635672.2228 # total power usage of icache_cc2
366
dcache_power_cc2       38877151.8273 # total power usage of dcache_cc2
367
dcache2_power_cc2      3985677.2888 # total power usage of dcache2_cc2
368
alu_power_cc2          19926183.4687 # total power usage of alu_cc2
369
resultbus_power_cc2    10053566.1958 # total power usage of resultbus_cc2
370
clock_power_cc2        98820978.7806 # total power usage of clock_cc2
371
avg_rename_power_cc2         0.0236 # avg power usage of rename unit_cc2
372
avg_bpred_power_cc2          0.0519 # avg power usage of bpred unit_cc2
373
avg_window_power_cc2         0.2143 # avg power usage of instruction window_cc2
374
avg_lsq_power_cc2            0.0276 # avg power usage of instruction lsq_cc2
375
avg_regfile_power_cc2        0.0918 # avg power usage of arch. regfile_cc2
376
avg_icache_power_cc2         0.2679 # avg power usage of icache_cc2
377
avg_dcache_power_cc2         0.5907 # avg power usage of dcache_cc2
378
avg_dcache2_power_cc2        0.0606 # avg power usage of dcache2_cc2
379
avg_alu_power_cc2            0.3027 # avg power usage of alu_cc2
380
avg_resultbus_power_cc2       0.1527 # avg power usage of resultbus_cc2
381
avg_clock_power_cc2          1.5014 # avg power usage of clock_cc2
382
fetch_stage_power_cc2  21051791.7246 # total power usage of fetch stage_cc2
383
dispatch_stage_power_cc2 1553634.6847 # total power usage of dispatch stage_cc2
384
issue_stage_power_cc2  88764805.5562 # total power usage of issue stage_cc2
385
avg_fetch_power_cc2          0.3198 # average power of fetch unit per cycle_cc2
386
avg_dispatch_power_cc2       0.0236 # average power of dispatch unit per cycle_cc2
387
avg_issue_power_cc2          1.3486 # average power of issue unit per cycle_cc2
388
total_power_cycle_cc2  216233512.0685 # total power per cycle_cc2
389
avg_total_power_cycle_cc2       3.2853 # average total power per cycle_cc2
390
avg_total_power_insn_cc2       3.0891 # average total power per insn_cc2
391
rename_power_cc3       1910166.2388 # total power usage of rename unit_cc3
392
bpred_power_cc3        10319512.5495 # total power usage of bpred unit_cc3
393
window_power_cc3       15674348.0762 # total power usage of instruction window_cc3
394
lsq_power_cc3          2819839.2283 # total power usage of lsq_cc3
395
regfile_power_cc3      9082789.7219 # total power usage of arch. regfile_cc3
396
icache_power_cc3       20289732.2780 # total power usage of icache_cc3
397
dcache_power_cc3       46965592.4451 # total power usage of dcache_cc3
398
dcache2_power_cc3      11563389.6378 # total power usage of dcache2_cc3
399
alu_power_cc3          48568434.6392 # total power usage of alu_cc3
400
resultbus_power_cc3    11804706.3405 # total power usage of resultbus_cc3
401
clock_power_cc3        151333899.7787 # total power usage of clock_cc3
402
avg_rename_power_cc3         0.0290 # avg power usage of rename unit_cc3
403
avg_bpred_power_cc3          0.1568 # avg power usage of bpred unit_cc3
404
avg_window_power_cc3         0.2381 # avg power usage of instruction window_cc3
405
avg_lsq_power_cc3            0.0428 # avg power usage of instruction lsq_cc3
406
avg_regfile_power_cc3        0.1380 # avg power usage of arch. regfile_cc3
407
avg_icache_power_cc3         0.3083 # avg power usage of icache_cc3
408
avg_dcache_power_cc3         0.7136 # avg power usage of dcache_cc3
409
avg_dcache2_power_cc3        0.1757 # avg power usage of dcache2_cc3
410
avg_alu_power_cc3            0.7379 # avg power usage of alu_cc3
411
avg_resultbus_power_cc3       0.1794 # avg power usage of resultbus_cc3
412
avg_clock_power_cc3          2.2993 # avg power usage of clock_cc3
413
fetch_stage_power_cc3  30609244.8275 # total power usage of fetch stage_cc3
414
dispatch_stage_power_cc3 1910166.2388 # total power usage of dispatch stage_cc3
415
issue_stage_power_cc3  137396310.3671 # total power usage of issue stage_cc3
416
avg_fetch_power_cc3          0.4651 # average power of fetch unit per cycle_cc3
417
avg_dispatch_power_cc3       0.0290 # average power of dispatch unit per cycle_cc3
418
avg_issue_power_cc3          2.0875 # average power of issue unit per cycle_cc3
419
total_power_cycle_cc3  330332410.9341 # total power per cycle_cc3
420
avg_total_power_cycle_cc3       5.0189 # average total power per cycle_cc3
421
avg_total_power_insn_cc3       4.7190 # average total power per insn_cc3
422
total_rename_access        69999518 # total number accesses of rename unit
423
total_bpred_access          5975253 # total number accesses of bpred unit
424
total_window_access       279747940 # total number accesses of instruction window
425
total_lsq_access           39263235 # total number accesses of load/store queue
426
total_regfile_access      106492746 # total number accesses of arch. regfile
427
total_icache_access        71933877 # total number accesses of icache
428
total_dcache_access        38966370 # total number accesses of dcache
429
total_dcache2_access        6474650 # total number accesses of dcache2
430
total_alu_access           66569109 # total number accesses of alu
431
total_resultbus_access     82011166 # total number accesses of resultbus
432
avg_rename_access            1.0635 # avg number accesses of rename unit
433
avg_bpred_access             0.0908 # avg number accesses of bpred unit
434
avg_window_access            4.2503 # avg number accesses of instruction window
435
avg_lsq_access               0.5965 # avg number accesses of lsq
436
avg_regfile_access           1.6180 # avg number accesses of arch. regfile
437
avg_icache_access            1.0929 # avg number accesses of icache
438
avg_dcache_access            0.5920 # avg number accesses of dcache
439
avg_dcache2_access           0.0984 # avg number accesses of dcache2
440
avg_alu_access               1.0114 # avg number accesses of alu
441
avg_resultbus_access         1.2460 # avg number accesses of resultbus
474 442
max_rename_access                 4 # max number accesses of rename unit
475 443
max_bpred_access                  4 # max number accesses of bpred unit
476
max_window_access                17 # max number accesses of instruction window
477
max_lsq_access                    6 # max number accesses of load/store queue
478
max_regfile_access               12 # max number accesses of arch. regfile
444
max_window_access                16 # max number accesses of instruction window
445
max_lsq_access                    5 # max number accesses of load/store queue
446
max_regfile_access               11 # max number accesses of arch. regfile
479 447
max_icache_access                 4 # max number accesses of icache
480 448
max_dcache_access                 4 # max number accesses of dcache
481
max_dcache2_access                5 # max number accesses of dcache2
449
max_dcache2_access                4 # max number accesses of dcache2
482 450
max_alu_access                    4 # max number accesses of alu
483
max_resultbus_access              9 # max number accesses of resultbus
451
max_resultbus_access              7 # max number accesses of resultbus
484 452
max_cycle_power_cc1         12.8305 # maximum cycle power usage of cc1
485
max_cycle_power_cc2          9.9448 # maximum cycle power usage of cc2
486
max_cycle_power_cc3         10.9548 # maximum cycle power usage of cc3
487
parasitic_power_cc1    25645316687.4515 # parasitic power cc1
488
parasitic_power_cc2    25645316687.4515 # parasitic power cc2
489
parasitic_power_cc3    25645316687.4515 # parasitic power cc3
453
max_cycle_power_cc2          9.8040 # maximum cycle power usage of cc2
454
max_cycle_power_cc3         10.8435 # maximum cycle power usage of cc3
455
parasitic_power_cc3    54153087.1180 # total parasitic power cc3
456
onchip parasitic_power_cc3 16454492.0000 # onchip parasitic power cc3
457
offchip parasitic_power_cc3 37698595.1180 # offchip parasitic power cc3
490 458
min amperage                 0.0000 # min amperage
491
max amperage                 5.7657 # max amperage
459
max amperage                 5.7071 # max amperage
492 460
slow_cycles                  0.0000 # slow cycles
493 461
fast_cycles                  0.0000 # fast cycles
494 462
sim_invalid_addrs                 0 # total non-speculative bogus addresses seen (debug var)
......
501 469
ld_prog_entry            0x00400140 # program entry point (initial PC)
502 470
ld_environ_base          0x7fff8000 # program environment base address address
503 471
ld_target_big_endian              0 # target executable endian-ness, non-zero if big endian
504
mem.page_count                49591 # total number of pages allocated
505
mem.page_mem                198364k # total size of memory pages allocated
506
mem.ptab_misses               90778 # total first level page table misses
507
mem.ptab_accesses      189233613744 # total page table accesses
508
mem.ptab_miss_rate           0.0000 # first level page table miss rate
472
mem.page_count                49588 # total number of pages allocated
473
mem.page_mem                198352k # total size of memory pages allocated
474
mem.ptab_misses               70367 # total first level page table misses
475
mem.ptab_accesses         243298880 # total page table accesses
476
mem.ptab_miss_rate           0.0003 # first level page table miss rate
509 477

  
510 478

  
511 479
Cache Parameters:

Also available in: Unified diff