Revision 60 spec/gcc/gcc_orig.txt

View differences:

gcc_orig.txt
62 62
 bitline_power (W): 0.83087
63 63
 senseamp_power (W): 0.14592
64 64
 tagarray_power (W): 0.147353
65
sim: command line: ./sim-outorder gcc00.O2unroll.gcc.100M.ss -funroll-loops -fforce-mem -fcse-follow-jumps -fcse-skip-blocks -fexpensive-optimizations -fstrength-reduce -fpeephole -fschedule-insns -finline-functions -fschedule-insns2 -O regclass.i -o regclass.s 
65
sim: command line: ./sim-outorder -max:inst 10000000 gcc00.O2unroll.gcc.100M.ss -funroll-loops -fforce-mem -fcse-follow-jumps -fcse-skip-blocks -fexpensive-optimizations -fstrength-reduce -fpeephole -fschedule-insns -finline-functions -fschedule-insns2 -O regclass.i -o regclass.s 
66 66

  
67
sim: simulation started @ Mon Nov 30 16:13:58 2009, options follow:
67
sim: simulation started @ Tue Dec  1 19:35:03 2009, options follow:
68 68

  
69 69
sim-outorder: This simulator implements a very detailed out-of-order issue
70 70
superscalar processor with a two-level memory system and speculative
......
83 83
# -redir:sim           <null> # redirect simulator output to file (non-interactive only)
84 84
# -redir:prog          <null> # redirect simulated program output to file
85 85
-nice                       0 # simulator scheduling priority
86
-max:inst                   0 # maximum number of inst's to execute
86
-max:inst            10000000 # maximum number of inst's to execute
87 87
-fastfwd                    0 # number of insts skipped before timing starts
88 88
# -ptrace              <null> # generate pipetrace, i.e., <fname|stdout|stderr> <range>
89 89
-fetch:ifqsize              4 # instruction fetch queue size (in insts)
......
188 188
sim: ** starting performance simulation **
189 189
warning: syscall: sigvec ignored
190 190
warning: syscall: sigvec ignored
191
 init_reg_sets init_reg_sets_1 fix_register reg_preferred_class reg_preferred_or_nothing regclass_init regclass reg_class_record record_address_regs reg_scan reg_scan_mark_refs
192
time in parse: 15.464966
193
time in integration: 1.220076
194
time in jump: 7.580472
195
time in cse: 23.113446
196
time in loop: 9.452590
197
time in cse2: 41.490594
198
time in flow: 6.820425
199
time in combine: 33.282081
200
time in sched: 9.000563
201
time in local-alloc: 11.676730
202
time in global-alloc: 12.232766
203
time in sched2: 6.980437
204
time in dbranch: 17.545095
205
time in shorten-branch: 0.388026
206
time in stack-reg: 0.000000
207
time in final: 7.112443
208
time in varconst: 0.216014
209
time in symout: 0.000000
210
time in dump: 0.000000
211

  
191
 init_reg_sets
212 192
sim: ** simulation statistics **
213
sim_num_insn              172200679 # total number of instructions committed
214
sim_num_refs               68343556 # total number of loads and stores committed
215
sim_num_loads              44498289 # total number of loads committed
216
sim_num_stores         23845267.0000 # total number of stores committed
217
sim_num_branches           35305345 # total number of branches committed
218
sim_elapsed_time                208 # total simulation time in seconds
219
sim_inst_rate           827887.8798 # simulation speed (in insts/sec)
220
sim_total_insn            201110265 # total number of instructions executed
221
sim_total_refs             79004211 # total number of loads and stores executed
222
sim_total_loads            53353323 # total number of loads executed
223
sim_total_stores       25650888.0000 # total number of stores executed
224
sim_total_branches         41270170 # total number of branches executed
225
sim_cycle                 185516905 # total simulation time in cycles
226
sim_IPC                      0.9282 # instructions per cycle
227
sim_CPI                      1.0773 # cycles per instruction
228
sim_exec_BW                  1.0841 # total instructions (mis-spec + committed) per cycle
229
sim_IPB                      4.8775 # instruction per branch
230
IFQ_count                 289260070 # cumulative IFQ occupancy
231
IFQ_fcount                 60074054 # cumulative IFQ full count
232
ifq_occupancy                1.5592 # avg IFQ occupancy (insn's)
233
ifq_rate                     1.0841 # avg IFQ dispatch rate (insn/cycle)
234
ifq_latency                  1.4383 # avg IFQ occupant latency (cycle's)
235
ifq_full                     0.3238 # fraction of time (cycle's) IFQ was full
236
RUU_count                1039737033 # cumulative RUU occupancy
237
RUU_fcount                 20165698 # cumulative RUU full count
238
ruu_occupancy                5.6045 # avg RUU occupancy (insn's)
239
ruu_rate                     1.0841 # avg RUU dispatch rate (insn/cycle)
240
ruu_latency                  5.1700 # avg RUU occupant latency (cycle's)
241
ruu_full                     0.1087 # fraction of time (cycle's) RUU was full
242
LSQ_count                 416172678 # cumulative LSQ occupancy
243
LSQ_fcount                 16765980 # cumulative LSQ full count
244
lsq_occupancy                2.2433 # avg LSQ occupancy (insn's)
245
lsq_rate                     1.0841 # avg LSQ dispatch rate (insn/cycle)
246
lsq_latency                  2.0694 # avg LSQ occupant latency (cycle's)
247
lsq_full                     0.0904 # fraction of time (cycle's) LSQ was full
248
bpred_bimod.lookups        43325430 # total number of bpred lookups
249
bpred_bimod.updates        35305345 # total number of updates
250
bpred_bimod.addr_hits      30829029 # total number of address-predicted hits
251
bpred_bimod.dir_hits       31597185 # total number of direction-predicted hits (includes addr-hits)
252
bpred_bimod.misses          3708160 # total number of misses
253
bpred_bimod.jr_hits         2853180 # total number of address-predicted hits for JR's
254
bpred_bimod.jr_seen         3578275 # total number of JR's seen
255
bpred_bimod.jr_non_ras_hits.PP       317354 # total number of address-predicted hits for non-RAS JR's
256
bpred_bimod.jr_non_ras_seen.PP       965369 # total number of non-RAS JR's seen
257
bpred_bimod.bpred_addr_rate    0.8732 # branch address-prediction rate (i.e., addr-hits/updates)
258
bpred_bimod.bpred_dir_rate    0.8950 # branch direction-prediction rate (i.e., all-hits/updates)
259
bpred_bimod.bpred_jr_rate    0.7974 # JR address-prediction rate (i.e., JR addr-hits/JRs seen)
260
bpred_bimod.bpred_jr_non_ras_rate.PP    0.3287 # non-RAS JR addr-pred rate (ie, non-RAS JR hits/JRs seen)
261
bpred_bimod.retstack_pushes      3240181 # total number of address pushed onto ret-addr stack
262
bpred_bimod.retstack_pops      3023017 # total number of address popped off of ret-addr stack
263
bpred_bimod.used_ras.PP      2612906 # total number of RAS predictions used
264
bpred_bimod.ras_hits.PP      2535826 # total number of RAS hits
265
bpred_bimod.ras_rate.PP    0.9705 # RAS prediction rate (i.e., RAS hits/used RAS)
266
il1.accesses              224882137 # total number of accesses
267
il1.hits                  210152805 # total number of hits
268
il1.misses                 14729332 # total number of misses
269
il1.replacements           14728820 # total number of replacements
193
sim_num_insn                8719943 # total number of instructions committed
194
sim_num_refs                3472792 # total number of loads and stores committed
195
sim_num_loads               2248866 # total number of loads committed
196
sim_num_stores         1223926.0000 # total number of stores committed
197
sim_num_branches            1812676 # total number of branches committed
198
sim_elapsed_time                 11 # total simulation time in seconds
199
sim_inst_rate           792722.0909 # simulation speed (in insts/sec)
200
sim_total_insn             10000000 # total number of instructions executed
201
sim_total_refs              3951118 # total number of loads and stores executed
202
sim_total_loads             2629542 # total number of loads executed
203
sim_total_stores       1321576.0000 # total number of stores executed
204
sim_total_branches          2093244 # total number of branches executed
205
sim_cycle                  10902054 # total simulation time in cycles
206
sim_IPC                      0.7998 # instructions per cycle
207
sim_CPI                      1.2502 # cycles per instruction
208
sim_exec_BW                  0.9173 # total instructions (mis-spec + committed) per cycle
209
sim_IPB                      4.8105 # instruction per branch
210
IFQ_count                  13738353 # cumulative IFQ occupancy
211
IFQ_fcount                  2733952 # cumulative IFQ full count
212
ifq_occupancy                1.2602 # avg IFQ occupancy (insn's)
213
ifq_rate                     0.9173 # avg IFQ dispatch rate (insn/cycle)
214
ifq_latency                  1.3738 # avg IFQ occupant latency (cycle's)
215
ifq_full                     0.2508 # fraction of time (cycle's) IFQ was full
216
RUU_count                  51435453 # cumulative RUU occupancy
217
RUU_fcount                   816180 # cumulative RUU full count
218
ruu_occupancy                4.7180 # avg RUU occupancy (insn's)
219
ruu_rate                     0.9173 # avg RUU dispatch rate (insn/cycle)
220
ruu_latency                  5.1435 # avg RUU occupant latency (cycle's)
221
ruu_full                     0.0749 # fraction of time (cycle's) RUU was full
222
LSQ_count                  20700795 # cumulative LSQ occupancy
223
LSQ_fcount                   716983 # cumulative LSQ full count
224
lsq_occupancy                1.8988 # avg LSQ occupancy (insn's)
225
lsq_rate                     0.9173 # avg LSQ dispatch rate (insn/cycle)
226
lsq_latency                  2.0701 # avg LSQ occupant latency (cycle's)
227
lsq_full                     0.0658 # fraction of time (cycle's) LSQ was full
228
bpred_bimod.lookups         2179972 # total number of bpred lookups
229
bpred_bimod.updates         1812675 # total number of updates
230
bpred_bimod.addr_hits       1584928 # total number of address-predicted hits
231
bpred_bimod.dir_hits        1633070 # total number of direction-predicted hits (includes addr-hits)
232
bpred_bimod.misses           179605 # total number of misses
233
bpred_bimod.jr_hits          161143 # total number of address-predicted hits for JR's
234
bpred_bimod.jr_seen          198743 # total number of JR's seen
235
bpred_bimod.jr_non_ras_hits.PP        22393 # total number of address-predicted hits for non-RAS JR's
236
bpred_bimod.jr_non_ras_seen.PP        54322 # total number of non-RAS JR's seen
237
bpred_bimod.bpred_addr_rate    0.8744 # branch address-prediction rate (i.e., addr-hits/updates)
238
bpred_bimod.bpred_dir_rate    0.9009 # branch direction-prediction rate (i.e., all-hits/updates)
239
bpred_bimod.bpred_jr_rate    0.8108 # JR address-prediction rate (i.e., JR addr-hits/JRs seen)
240
bpred_bimod.bpred_jr_non_ras_rate.PP    0.4122 # non-RAS JR addr-pred rate (ie, non-RAS JR hits/JRs seen)
241
bpred_bimod.retstack_pushes       175081 # total number of address pushed onto ret-addr stack
242
bpred_bimod.retstack_pops       165005 # total number of address popped off of ret-addr stack
243
bpred_bimod.used_ras.PP       144421 # total number of RAS predictions used
244
bpred_bimod.ras_hits.PP       138750 # total number of RAS hits
245
bpred_bimod.ras_rate.PP    0.9607 # RAS prediction rate (i.e., RAS hits/used RAS)
246
il1.accesses               11367480 # total number of accesses
247
il1.hits                   10380169 # total number of hits
248
il1.misses                   987311 # total number of misses
249
il1.replacements             986799 # total number of replacements
270 250
il1.writebacks                    0 # total number of writebacks
271 251
il1.invalidations                 0 # total number of invalidations
272
il1.miss_rate                0.0655 # miss rate (i.e., misses/ref)
273
il1.repl_rate                0.0655 # replacement rate (i.e., repls/ref)
252
il1.miss_rate                0.0869 # miss rate (i.e., misses/ref)
253
il1.repl_rate                0.0868 # replacement rate (i.e., repls/ref)
274 254
il1.wb_rate                  0.0000 # writeback rate (i.e., wrbks/ref)
275 255
il1.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)
276
dl1.accesses               71738947 # total number of accesses
277
dl1.hits                   70588778 # total number of hits
278
dl1.misses                  1150169 # total number of misses
279
dl1.replacements            1149657 # total number of replacements
280
dl1.writebacks               351145 # total number of writebacks
256
dl1.accesses                3613728 # total number of accesses
257
dl1.hits                    3552399 # total number of hits
258
dl1.misses                    61329 # total number of misses
259
dl1.replacements              60817 # total number of replacements
260
dl1.writebacks                23182 # total number of writebacks
281 261
dl1.invalidations                 0 # total number of invalidations
282
dl1.miss_rate                0.0160 # miss rate (i.e., misses/ref)
283
dl1.repl_rate                0.0160 # replacement rate (i.e., repls/ref)
284
dl1.wb_rate                  0.0049 # writeback rate (i.e., wrbks/ref)
262
dl1.miss_rate                0.0170 # miss rate (i.e., misses/ref)
263
dl1.repl_rate                0.0168 # replacement rate (i.e., repls/ref)
264
dl1.wb_rate                  0.0064 # writeback rate (i.e., wrbks/ref)
285 265
dl1.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)
286
ul2.accesses               16230646 # total number of accesses
287
ul2.hits                   15915666 # total number of hits
288
ul2.misses                   314980 # total number of misses
289
ul2.replacements             310884 # total number of replacements
290
ul2.writebacks                57635 # total number of writebacks
266
ul2.accesses                1071822 # total number of accesses
267
ul2.hits                    1046170 # total number of hits
268
ul2.misses                    25652 # total number of misses
269
ul2.replacements              21556 # total number of replacements
270
ul2.writebacks                 5423 # total number of writebacks
291 271
ul2.invalidations                 0 # total number of invalidations
292
ul2.miss_rate                0.0194 # miss rate (i.e., misses/ref)
293
ul2.repl_rate                0.0192 # replacement rate (i.e., repls/ref)
294
ul2.wb_rate                  0.0036 # writeback rate (i.e., wrbks/ref)
272
ul2.miss_rate                0.0239 # miss rate (i.e., misses/ref)
273
ul2.repl_rate                0.0201 # replacement rate (i.e., repls/ref)
274
ul2.wb_rate                  0.0051 # writeback rate (i.e., wrbks/ref)
295 275
ul2.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)
296
itlb.accesses             224882137 # total number of accesses
297
itlb.hits                 224791405 # total number of hits
298
itlb.misses                   90732 # total number of misses
299
itlb.replacements             90668 # total number of replacements
276
itlb.accesses              11367480 # total number of accesses
277
itlb.hits                  11355781 # total number of hits
278
itlb.misses                   11699 # total number of misses
279
itlb.replacements             11635 # total number of replacements
300 280
itlb.writebacks                   0 # total number of writebacks
301 281
itlb.invalidations                0 # total number of invalidations
302
itlb.miss_rate               0.0004 # miss rate (i.e., misses/ref)
303
itlb.repl_rate               0.0004 # replacement rate (i.e., repls/ref)
282
itlb.miss_rate               0.0010 # miss rate (i.e., misses/ref)
283
itlb.repl_rate               0.0010 # replacement rate (i.e., repls/ref)
304 284
itlb.wb_rate                 0.0000 # writeback rate (i.e., wrbks/ref)
305 285
itlb.inv_rate                0.0000 # invalidation rate (i.e., invs/ref)
306
dtlb.accesses              72156358 # total number of accesses
307
dtlb.hits                  72154170 # total number of hits
308
dtlb.misses                    2188 # total number of misses
309
dtlb.replacements              2060 # total number of replacements
286
dtlb.accesses               3646802 # total number of accesses
287
dtlb.hits                   3646589 # total number of hits
288
dtlb.misses                     213 # total number of misses
289
dtlb.replacements                89 # total number of replacements
310 290
dtlb.writebacks                   0 # total number of writebacks
311 291
dtlb.invalidations                0 # total number of invalidations
312
dtlb.miss_rate               0.0000 # miss rate (i.e., misses/ref)
292
dtlb.miss_rate               0.0001 # miss rate (i.e., misses/ref)
313 293
dtlb.repl_rate               0.0000 # replacement rate (i.e., repls/ref)
314 294
dtlb.wb_rate                 0.0000 # writeback rate (i.e., wrbks/ref)
315 295
dtlb.inv_rate                0.0000 # invalidation rate (i.e., invs/ref)
316
rename_power           16470141.9026 # total power usage of rename unit
317
bpred_power            212124211.5734 # total power usage of bpred unit
318
window_power           96011717.5794 # total power usage of instruction window
319
lsq_power              37429548.8516 # total power usage of load/store queue
320
regfile_power          142831198.0535 # total power usage of arch. regfile
321
icache_power           124516839.4225 # total power usage of icache
322
dcache_power           370184282.6854 # total power usage of dcache
323
dcache2_power          228401693.6754 # total power usage of dcache2
324
alu_power              902825281.9901 # total power usage of alu
325
falu_power             680701603.0320 # total power usage of falu
326
resultbus_power        92645733.3963 # total power usage of resultbus
327
clock_power            1877416637.3875 # total power usage of clock
296
rename_power            967881.4778 # total power usage of rename unit
297
bpred_power            12465654.3537 # total power usage of bpred unit
298
window_power           5642207.8086 # total power usage of instruction window
299
lsq_power              2199578.3245 # total power usage of load/store queue
300
regfile_power          8393593.2278 # total power usage of arch. regfile
301
icache_power           7317334.8351 # total power usage of icache
302
dcache_power           21754184.8818 # total power usage of dcache
303
dcache2_power          13422214.0261 # total power usage of dcache2
304
alu_power              53055272.8492 # total power usage of alu
305
falu_power             40001991.4249 # total power usage of falu
306
resultbus_power        5444402.9746 # total power usage of resultbus
307
clock_power            110327937.5607 # total power usage of clock
328 308
avg_rename_power             0.0888 # avg power usage of rename unit
329 309
avg_bpred_power              1.1434 # avg power usage of bpred unit
330 310
avg_window_power             0.5175 # avg power usage of instruction window
......
337 317
avg_falu_power               3.6692 # avg power usage of falu
338 318
avg_resultbus_power          0.4994 # avg power usage of resultbus
339 319
avg_clock_power             10.1199 # avg power usage of clock
340
fetch_stage_power      336641050.9959 # total power usage of fetch stage
341
dispatch_stage_power   16470141.9026 # total power usage of dispatch stage
342
issue_stage_power      1727498258.1783 # total power usage of issue stage
320
fetch_stage_power      19782989.1888 # total power usage of fetch stage
321
dispatch_stage_power    967881.4778 # total power usage of dispatch stage
322
issue_stage_power      101517860.8647 # total power usage of issue stage
343 323
avg_fetch_power              1.8146 # average power of fetch unit per cycle
344 324
avg_dispatch_power           0.0888 # average power of dispatch unit per cycle
345 325
avg_issue_power              9.3118 # average power of issue unit per cycle
346
total_power            4100857286.5178 # total power per cycle
326
total_power            240990262.3198 # total power per cycle
347 327
avg_total_power_cycle       22.1050 # average total power per cycle
348 328
avg_total_power_cycle_nofp_nod2      17.2047 # average total power per cycle
349
avg_total_power_insn        20.3911 # average total power per insn
350
avg_total_power_insn_nofp_nod2      15.8707 # average total power per insn
351
rename_power_cc1       6255367.5696 # total power usage of rename unit_cc1
352
bpred_power_cc1        33922564.4640 # total power usage of bpred unit_cc1
353
window_power_cc1       61689071.5993 # total power usage of instruction window_cc1
354
lsq_power_cc1          4932853.0010 # total power usage of lsq_cc1
355
regfile_power_cc1      69046167.5108 # total power usage of arch. regfile_cc1
356
icache_power_cc1       56747432.6709 # total power usage of icache_cc1
357
dcache_power_cc1       98161450.7489 # total power usage of dcache_cc1
358
dcache2_power_cc1      19493839.1810 # total power usage of dcache2_cc1
359
alu_power_cc1          98850959.1105 # total power usage of alu_cc1
360
resultbus_power_cc1    42967212.4817 # total power usage of resultbus_cc1
361
clock_power_cc1        438683281.2330 # total power usage of clock_cc1
362
avg_rename_power_cc1         0.0337 # avg power usage of rename unit_cc1
363
avg_bpred_power_cc1          0.1829 # avg power usage of bpred unit_cc1
364
avg_window_power_cc1         0.3325 # avg power usage of instruction window_cc1
365
avg_lsq_power_cc1            0.0266 # avg power usage of lsq_cc1
366
avg_regfile_power_cc1        0.3722 # avg power usage of arch. regfile_cc1
367
avg_icache_power_cc1         0.3059 # avg power usage of icache_cc1
368
avg_dcache_power_cc1         0.5291 # avg power usage of dcache_cc1
369
avg_dcache2_power_cc1        0.1051 # avg power usage of dcache2_cc1
370
avg_alu_power_cc1            0.5328 # avg power usage of alu_cc1
371
avg_resultbus_power_cc1       0.2316 # avg power usage of resultbus_cc1
372
avg_clock_power_cc1          2.3647 # avg power usage of clock_cc1
373
fetch_stage_power_cc1  90669997.1349 # total power usage of fetch stage_cc1
374
dispatch_stage_power_cc1 6255367.5696 # total power usage of dispatch stage_cc1
375
issue_stage_power_cc1  326095386.1224 # total power usage of issue stage_cc1
376
avg_fetch_power_cc1          0.4887 # average power of fetch unit per cycle_cc1
377
avg_dispatch_power_cc1       0.0337 # average power of dispatch unit per cycle_cc1
378
avg_issue_power_cc1          1.7578 # average power of issue unit per cycle_cc1
379
total_power_cycle_cc1  930750199.5707 # total power per cycle_cc1
380
avg_total_power_cycle_cc1       5.0171 # average total power per cycle_cc1
381
avg_total_power_insn_cc1       4.6281 # average total power per insn_cc1
382
rename_power_cc2       4449755.9489 # total power usage of rename unit_cc2
383
bpred_power_cc2        20184463.7519 # total power usage of bpred unit_cc2
384
window_power_cc2       37365036.6849 # total power usage of instruction window_cc2
385
lsq_power_cc2          3406654.5071 # total power usage of lsq_cc2
386
regfile_power_cc2      14719209.8716 # total power usage of arch. regfile_cc2
387
icache_power_cc2       56747432.6709 # total power usage of icache_cc2
388
dcache_power_cc2       71574692.0482 # total power usage of dcache_cc2
389
dcache2_power_cc2      9991291.7505 # total power usage of dcache2_cc2
390
alu_power_cc2          54166582.3126 # total power usage of alu_cc2
391
resultbus_power_cc2    23934468.8636 # total power usage of resultbus_cc2
392
clock_power_cc2        264877804.5740 # total power usage of clock_cc2
393
avg_rename_power_cc2         0.0240 # avg power usage of rename unit_cc2
394
avg_bpred_power_cc2          0.1088 # avg power usage of bpred unit_cc2
395
avg_window_power_cc2         0.2014 # avg power usage of instruction window_cc2
396
avg_lsq_power_cc2            0.0184 # avg power usage of instruction lsq_cc2
397
avg_regfile_power_cc2        0.0793 # avg power usage of arch. regfile_cc2
398
avg_icache_power_cc2         0.3059 # avg power usage of icache_cc2
399
avg_dcache_power_cc2         0.3858 # avg power usage of dcache_cc2
400
avg_dcache2_power_cc2        0.0539 # avg power usage of dcache2_cc2
401
avg_alu_power_cc2            0.2920 # avg power usage of alu_cc2
402
avg_resultbus_power_cc2       0.1290 # avg power usage of resultbus_cc2
403
avg_clock_power_cc2          1.4278 # avg power usage of clock_cc2
404
fetch_stage_power_cc2  76931896.4228 # total power usage of fetch stage_cc2
405
dispatch_stage_power_cc2 4449755.9489 # total power usage of dispatch stage_cc2
406
issue_stage_power_cc2  200438726.1668 # total power usage of issue stage_cc2
407
avg_fetch_power_cc2          0.4147 # average power of fetch unit per cycle_cc2
408
avg_dispatch_power_cc2       0.0240 # average power of dispatch unit per cycle_cc2
409
avg_issue_power_cc2          1.0804 # average power of issue unit per cycle_cc2
410
total_power_cycle_cc2  561417392.9841 # total power per cycle_cc2
411
avg_total_power_cycle_cc2       3.0262 # average total power per cycle_cc2
412
avg_total_power_insn_cc2       2.7916 # average total power per insn_cc2
413
rename_power_cc3       5471233.3871 # total power usage of rename unit_cc3
414
bpred_power_cc3        38035307.2647 # total power usage of bpred unit_cc3
415
window_power_cc3       40548570.1362 # total power usage of instruction window_cc3
416
lsq_power_cc3          6632040.4057 # total power usage of lsq_cc3
417
regfile_power_cc3      21484896.1788 # total power usage of arch. regfile_cc3
418
icache_power_cc3       63524373.2445 # total power usage of icache_cc3
419
dcache_power_cc3       99005370.7658 # total power usage of dcache_cc3
420
dcache2_power_cc3      30883485.3575 # total power usage of dcache2_cc3
421
alu_power_cc3          134564015.2650 # total power usage of alu_cc3
422
resultbus_power_cc3    28782864.8730 # total power usage of resultbus_cc3
423
clock_power_cc3        408044203.0867 # total power usage of clock_cc3
424
avg_rename_power_cc3         0.0295 # avg power usage of rename unit_cc3
425
avg_bpred_power_cc3          0.2050 # avg power usage of bpred unit_cc3
426
avg_window_power_cc3         0.2186 # avg power usage of instruction window_cc3
427
avg_lsq_power_cc3            0.0357 # avg power usage of instruction lsq_cc3
428
avg_regfile_power_cc3        0.1158 # avg power usage of arch. regfile_cc3
429
avg_icache_power_cc3         0.3424 # avg power usage of icache_cc3
430
avg_dcache_power_cc3         0.5337 # avg power usage of dcache_cc3
431
avg_dcache2_power_cc3        0.1665 # avg power usage of dcache2_cc3
432
avg_alu_power_cc3            0.7253 # avg power usage of alu_cc3
433
avg_resultbus_power_cc3       0.1551 # avg power usage of resultbus_cc3
434
avg_clock_power_cc3          2.1995 # avg power usage of clock_cc3
435
fetch_stage_power_cc3  101559680.5093 # total power usage of fetch stage_cc3
436
dispatch_stage_power_cc3 5471233.3871 # total power usage of dispatch stage_cc3
437
issue_stage_power_cc3  340416346.8032 # total power usage of issue stage_cc3
438
avg_fetch_power_cc3          0.5474 # average power of fetch unit per cycle_cc3
439
avg_dispatch_power_cc3       0.0295 # average power of dispatch unit per cycle_cc3
440
avg_issue_power_cc3          1.8350 # average power of issue unit per cycle_cc3
441
total_power_cycle_cc3  876976359.9651 # total power per cycle_cc3
442
avg_total_power_cycle_cc3       4.7272 # average total power per cycle_cc3
443
avg_total_power_insn_cc3       4.3607 # average total power per insn_cc3
444
total_rename_access       200485207 # total number accesses of rename unit
445
total_bpred_access         35305345 # total number accesses of bpred unit
446
total_window_access       729803289 # total number accesses of instruction window
447
total_lsq_access           73117408 # total number accesses of load/store queue
448
total_regfile_access      254805012 # total number accesses of arch. regfile
449
total_icache_access       225607983 # total number accesses of icache
450
total_dcache_access        71738947 # total number accesses of dcache
451
total_dcache2_access       16230646 # total number accesses of dcache2
452
total_alu_access          180946144 # total number accesses of alu
453
total_resultbus_access    196891185 # total number accesses of resultbus
454
avg_rename_access            1.0807 # avg number accesses of rename unit
455
avg_bpred_access             0.1903 # avg number accesses of bpred unit
456
avg_window_access            3.9339 # avg number accesses of instruction window
457
avg_lsq_access               0.3941 # avg number accesses of lsq
458
avg_regfile_access           1.3735 # avg number accesses of arch. regfile
459
avg_icache_access            1.2161 # avg number accesses of icache
460
avg_dcache_access            0.3867 # avg number accesses of dcache
461
avg_dcache2_access           0.0875 # avg number accesses of dcache2
462
avg_alu_access               0.9754 # avg number accesses of alu
463
avg_resultbus_access         1.0613 # avg number accesses of resultbus
329
avg_total_power_insn        24.0990 # average total power per insn
330
avg_total_power_insn_nofp_nod2      18.7566 # average total power per insn
331
rename_power_cc1        312975.6478 # total power usage of rename unit_cc1
332
bpred_power_cc1        1772654.8351 # total power usage of bpred unit_cc1
333
window_power_cc1       3371208.2019 # total power usage of instruction window_cc1
334
lsq_power_cc1           254955.0582 # total power usage of lsq_cc1
335
regfile_power_cc1      3726732.5201 # total power usage of arch. regfile_cc1
336
icache_power_cc1       2949453.9247 # total power usage of icache_cc1
337
dcache_power_cc1       5005768.3915 # total power usage of dcache_cc1
338
dcache2_power_cc1      1288371.6533 # total power usage of dcache2_cc1
339
alu_power_cc1          5146239.6867 # total power usage of alu_cc1
340
resultbus_power_cc1    2238865.7845 # total power usage of resultbus_cc1
341
clock_power_cc1        24625365.4139 # total power usage of clock_cc1
342
avg_rename_power_cc1         0.0287 # avg power usage of rename unit_cc1
343
avg_bpred_power_cc1          0.1626 # avg power usage of bpred unit_cc1
344
avg_window_power_cc1         0.3092 # avg power usage of instruction window_cc1
345
avg_lsq_power_cc1            0.0234 # avg power usage of lsq_cc1
346
avg_regfile_power_cc1        0.3418 # avg power usage of arch. regfile_cc1
347
avg_icache_power_cc1         0.2705 # avg power usage of icache_cc1
348
avg_dcache_power_cc1         0.4592 # avg power usage of dcache_cc1
349
avg_dcache2_power_cc1        0.1182 # avg power usage of dcache2_cc1
350
avg_alu_power_cc1            0.4720 # avg power usage of alu_cc1
351
avg_resultbus_power_cc1       0.2054 # avg power usage of resultbus_cc1
352
avg_clock_power_cc1          2.2588 # avg power usage of clock_cc1
353
fetch_stage_power_cc1  4722108.7598 # total power usage of fetch stage_cc1
354
dispatch_stage_power_cc1  312975.6478 # total power usage of dispatch stage_cc1
355
issue_stage_power_cc1  17305408.7760 # total power usage of issue stage_cc1
356
avg_fetch_power_cc1          0.4331 # average power of fetch unit per cycle_cc1
357
avg_dispatch_power_cc1       0.0287 # average power of dispatch unit per cycle_cc1
358
avg_issue_power_cc1          1.5874 # average power of issue unit per cycle_cc1
359
total_power_cycle_cc1  50692591.1175 # total power per cycle_cc1
360
avg_total_power_cycle_cc1       4.6498 # average total power per cycle_cc1
361
avg_total_power_insn_cc1       5.0693 # average total power per insn_cc1
362
rename_power_cc2        221161.7310 # total power usage of rename unit_cc2
363
bpred_power_cc2        1036326.7327 # total power usage of bpred unit_cc2
364
window_power_cc2       1873345.0308 # total power usage of instruction window_cc2
365
lsq_power_cc2           173553.1792 # total power usage of lsq_cc2
366
regfile_power_cc2       737402.4659 # total power usage of arch. regfile_cc2
367
icache_power_cc2       2949453.9247 # total power usage of icache_cc2
368
dcache_power_cc2       3605453.9369 # total power usage of dcache_cc2
369
dcache2_power_cc2       659794.2133 # total power usage of dcache2_cc2
370
alu_power_cc2          2699263.2228 # total power usage of alu_cc2
371
resultbus_power_cc2    1192587.7424 # total power usage of resultbus_cc2
372
clock_power_cc2        14570297.5307 # total power usage of clock_cc2
373
avg_rename_power_cc2         0.0203 # avg power usage of rename unit_cc2
374
avg_bpred_power_cc2          0.0951 # avg power usage of bpred unit_cc2
375
avg_window_power_cc2         0.1718 # avg power usage of instruction window_cc2
376
avg_lsq_power_cc2            0.0159 # avg power usage of instruction lsq_cc2
377
avg_regfile_power_cc2        0.0676 # avg power usage of arch. regfile_cc2
378
avg_icache_power_cc2         0.2705 # avg power usage of icache_cc2
379
avg_dcache_power_cc2         0.3307 # avg power usage of dcache_cc2
380
avg_dcache2_power_cc2        0.0605 # avg power usage of dcache2_cc2
381
avg_alu_power_cc2            0.2476 # avg power usage of alu_cc2
382
avg_resultbus_power_cc2       0.1094 # avg power usage of resultbus_cc2
383
avg_clock_power_cc2          1.3365 # avg power usage of clock_cc2
384
fetch_stage_power_cc2  3985780.6573 # total power usage of fetch stage_cc2
385
dispatch_stage_power_cc2  221161.7310 # total power usage of dispatch stage_cc2
386
issue_stage_power_cc2  10203997.3254 # total power usage of issue stage_cc2
387
avg_fetch_power_cc2          0.3656 # average power of fetch unit per cycle_cc2
388
avg_dispatch_power_cc2       0.0203 # average power of dispatch unit per cycle_cc2
389
avg_issue_power_cc2          0.9360 # average power of issue unit per cycle_cc2
390
total_power_cycle_cc2  29718639.7103 # total power per cycle_cc2
391
avg_total_power_cycle_cc2       2.7260 # average total power per cycle_cc2
392
avg_total_power_insn_cc2       2.9719 # average total power per insn_cc2
393
rename_power_cc3        286652.3140 # total power usage of rename unit_cc3
394
bpred_power_cc3        2106951.6818 # total power usage of bpred unit_cc3
395
window_power_cc3       2084963.8708 # total power usage of instruction window_cc3
396
lsq_power_cc3           366697.3026 # total power usage of lsq_cc3
397
regfile_power_cc3      1171221.2043 # total power usage of arch. regfile_cc3
398
icache_power_cc3       3386242.0160 # total power usage of icache_cc3
399
dcache_power_cc3       5291187.7897 # total power usage of dcache_cc3
400
dcache2_power_cc3      1873261.6160 # total power usage of dcache2_cc3
401
alu_power_cc3          7490166.5392 # total power usage of alu_cc3
402
resultbus_power_cc3    1505982.0958 # total power usage of resultbus_cc3
403
clock_power_cc3        23095812.6117 # total power usage of clock_cc3
404
avg_rename_power_cc3         0.0263 # avg power usage of rename unit_cc3
405
avg_bpred_power_cc3          0.1933 # avg power usage of bpred unit_cc3
406
avg_window_power_cc3         0.1912 # avg power usage of instruction window_cc3
407
avg_lsq_power_cc3            0.0336 # avg power usage of instruction lsq_cc3
408
avg_regfile_power_cc3        0.1074 # avg power usage of arch. regfile_cc3
409
avg_icache_power_cc3         0.3106 # avg power usage of icache_cc3
410
avg_dcache_power_cc3         0.4853 # avg power usage of dcache_cc3
411
avg_dcache2_power_cc3        0.1718 # avg power usage of dcache2_cc3
412
avg_alu_power_cc3            0.6870 # avg power usage of alu_cc3
413
avg_resultbus_power_cc3       0.1381 # avg power usage of resultbus_cc3
414
avg_clock_power_cc3          2.1185 # avg power usage of clock_cc3
415
fetch_stage_power_cc3  5493193.6978 # total power usage of fetch stage_cc3
416
dispatch_stage_power_cc3  286652.3140 # total power usage of dispatch stage_cc3
417
issue_stage_power_cc3  18612259.2141 # total power usage of issue stage_cc3
418
avg_fetch_power_cc3          0.5039 # average power of fetch unit per cycle_cc3
419
avg_dispatch_power_cc3       0.0263 # average power of dispatch unit per cycle_cc3
420
avg_issue_power_cc3          1.7072 # average power of issue unit per cycle_cc3
421
total_power_cycle_cc3  48659139.0419 # total power per cycle_cc3
422
avg_total_power_cycle_cc3       4.4633 # average total power per cycle_cc3
423
avg_total_power_insn_cc3       4.8659 # average total power per insn_cc3
424
total_rename_access         9964514 # total number accesses of rename unit
425
total_bpred_access          1812675 # total number accesses of bpred unit
426
total_window_access        36517951 # total number accesses of instruction window
427
total_lsq_access            3703035 # total number accesses of load/store queue
428
total_regfile_access       12733497 # total number accesses of arch. regfile
429
total_icache_access        11409066 # total number accesses of icache
430
total_dcache_access         3613728 # total number accesses of dcache
431
total_dcache2_access        1071822 # total number accesses of dcache2
432
total_alu_access            9017660 # total number accesses of alu
433
total_resultbus_access      9833635 # total number accesses of resultbus
434
avg_rename_access            0.9140 # avg number accesses of rename unit
435
avg_bpred_access             0.1663 # avg number accesses of bpred unit
436
avg_window_access            3.3496 # avg number accesses of instruction window
437
avg_lsq_access               0.3397 # avg number accesses of lsq
438
avg_regfile_access           1.1680 # avg number accesses of arch. regfile
439
avg_icache_access            1.0465 # avg number accesses of icache
440
avg_dcache_access            0.3315 # avg number accesses of dcache
441
avg_dcache2_access           0.0983 # avg number accesses of dcache2
442
avg_alu_access               0.8272 # avg number accesses of alu
443
avg_resultbus_access         0.9020 # avg number accesses of resultbus
464 444
max_rename_access                 4 # max number accesses of rename unit
465 445
max_bpred_access                  4 # max number accesses of bpred unit
466
max_window_access                17 # max number accesses of instruction window
446
max_window_access                16 # max number accesses of instruction window
467 447
max_lsq_access                    6 # max number accesses of load/store queue
468 448
max_regfile_access               12 # max number accesses of arch. regfile
469 449
max_icache_access                 4 # max number accesses of icache
470 450
max_dcache_access                 4 # max number accesses of dcache
471
max_dcache2_access                7 # max number accesses of dcache2
451
max_dcache2_access                6 # max number accesses of dcache2
472 452
max_alu_access                    4 # max number accesses of alu
473 453
max_resultbus_access              8 # max number accesses of resultbus
474
max_cycle_power_cc1         12.1199 # maximum cycle power usage of cc1
475
max_cycle_power_cc2          9.6089 # maximum cycle power usage of cc2
476
max_cycle_power_cc3         10.7516 # maximum cycle power usage of cc3
477
parasitic_power_cc1    100996684.9694 # parasitic power cc1
478
parasitic_power_cc2    100996684.9694 # parasitic power cc2
479
parasitic_power_cc3    100996684.9694 # parasitic power cc3
454
max_cycle_power_cc1         12.0118 # maximum cycle power usage of cc1
455
max_cycle_power_cc2          9.2141 # maximum cycle power usage of cc2
456
max_cycle_power_cc3         10.3187 # maximum cycle power usage of cc3
457
parasitic_power_cc3    8549840.1295 # total parasitic power cc3
458
onchip parasitic_power_cc3 2725513.5000 # onchip parasitic power cc3
459
offchip parasitic_power_cc3 5824326.6295 # offchip parasitic power cc3
480 460
min amperage                 0.0000 # min amperage
481
max amperage                 5.6587 # max amperage
461
max amperage                 5.4309 # max amperage
482 462
slow_cycles                  0.0000 # slow cycles
483 463
fast_cycles                  0.0000 # fast cycles
484 464
sim_invalid_addrs                 0 # total non-speculative bogus addresses seen (debug var)
......
491 471
ld_prog_entry            0x00400140 # program entry point (initial PC)
492 472
ld_environ_base          0x7fff8000 # program environment base address address
493 473
ld_target_big_endian              0 # target executable endian-ness, non-zero if big endian
494
mem.page_count                  873 # total number of pages allocated
495
mem.page_mem                  3492k # total size of memory pages allocated
496
mem.ptab_misses                9978 # total first level page table misses
497
mem.ptab_accesses         609996197 # total page table accesses
474
mem.page_count                  765 # total number of pages allocated
475
mem.page_mem                  3060k # total size of memory pages allocated
476
mem.ptab_misses                1077 # total first level page table misses
477
mem.ptab_accesses          37143526 # total page table accesses
498 478
mem.ptab_miss_rate           0.0000 # first level page table miss rate
499 479

  
500 480

  

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