18743 - Energy Aware Computing

sim-outorder: SimpleScalar/PISA Tool Set version 3.0 of September, 1998.

Copyright (c) 1994-1998 by Todd M. Austin.  All Rights Reserved.

Processor Parameters:

Issue Width: 4

Window Size: 16

Number of Virtual Registers: 32

Number of Physical Registers: 16

Datapath Width: 64

Total Power Consumption: 24.105

Branch Predictor Power Consumption: 1.14342  (5.17%)

 branch target buffer power (W): 1.04097

 local predict power (W): 0.0275244

 global predict power (W): 0.031332

 chooser power (W): 0.0206036

 RAS power (W): 0.0229956

Rename Logic Power Consumption: 0.0887797  (0.402%)

 Instruction Decode Power (W): 0.0038821

 RAT decode_power (W): 0.0273861

 RAT wordline_power (W): 0.00645964

 RAT bitline_power (W): 0.0486255

 DCL Comparators (W): 0.0024263

Instruction Window Power Consumption: 0.517536  (2.34%)

 tagdrive (W): 0.0186418

 tagmatch (W): 0.00697769

 Selection Logic (W): 0.00331194

 decode_power (W): 0.0131921

 wordline_power (W): 0.0176803

 bitline_power (W): 0.457732

Load/Store Queue Power Consumption: 0.201758  (0.913%)

 tagdrive (W): 0.0854673

 tagmatch (W): 0.0207657

 decode_power (W): 0.00194105

 wordline_power (W): 0.00302882

 bitline_power (W): 0.0905553

Arch. Register File Power Consumption: 0.769909  (3.48%)

 decode_power (W): 0.0273861

 wordline_power (W): 0.0176803

 bitline_power (W): 0.724843

Result Bus Power Consumption: 0.499392  (2.26%)

Total Clock Power: 10.1199  (45.8%)

Int ALU Power: 1.19732  (5.42%)

FP ALU Power: 3.66922  (16.6%)

Instruction Cache Power Consumption: 0.614638  (2.78%)

 decode_power (W): 0.186809

 wordline_power (W): 0.00542611

 bitline_power (W): 0.231588

 senseamp_power (W): 0.07296

 tagarray_power (W): 0.117856

Itlb_power (W): 0.0565504 (0.256%)

Data Cache Power Consumption: 1.80232  (8.15%)

 decode_power (W): 0.15387

 wordline_power (W): 0.0368784

 bitline_power (W): 0.749615

 senseamp_power (W): 0.58368

 tagarray_power (W): 0.278274

Dtlb_power (W): 0.193103 (0.874%)

Level 2 Cache Power Consumption: 1.23116 (5.57%)

 decode_power (W): 0.0990259

 wordline_power (W): 0.00799512

 bitline_power (W): 0.83087

 senseamp_power (W): 0.14592

 tagarray_power (W): 0.147353

sim: command line: ./sim-outorder -max:inst 10000000 bzip200.O2unroll.gcc.100M.ss input.source 

sim: simulation started @ Mon Nov 30 12:03:47 2009, options follow:

sim-outorder: This simulator implements a very detailed out-of-order issue

superscalar processor with a two-level memory system and speculative

execution support.  This simulator is a performance simulator, tracking the

latency of all pipeline operations.

# -config                     # load configuration from a file

# -dumpconfig                 # dump configuration to a file

# -h                    false # print help message    

# -v                    false # verbose operation     

# -d                    false # enable debug message  

# -i                    false # start in Dlite debugger

-seed                       1 # random number generator seed (0 for timer seed)

# -q                    false # initialize and terminate immediately

# -chkpt               <null> # restore EIO trace execution from <fname>

# -redir:sim           <null> # redirect simulator output to file (non-interactive only)

# -redir:prog          <null> # redirect simulated program output to file

-nice                       0 # simulator scheduling priority

-max:inst            10000000 # maximum number of inst's to execute

-fastfwd                    0 # number of insts skipped before timing starts

# -ptrace              <null> # generate pipetrace, i.e., <fname|stdout|stderr> <range>

-fetch:ifqsize              4 # instruction fetch queue size (in insts)

-fetch:mplat                3 # extra branch mis-prediction latency

-fetch:speed                1 # speed of front-end of machine relative to execution core

-bpred                  bimod # branch predictor type {nottaken|taken|perfect|bimod|2lev|comb}

-bpred:bimod     2048 # bimodal predictor config (<table size>)

-bpred:2lev      1 1024 8 0 # 2-level predictor config (<l1size> <l2size> <hist_size> <xor>)

-bpred:comb      1024 # combining predictor config (<meta_table_size>)

-bpred:ras                  8 # return address stack size (0 for no return stack)

-bpred:btb       512 4 # BTB config (<num_sets> <associativity>)

# -bpred:spec_update       <null> # speculative predictors update in {ID|WB} (default non-spec)

-decode:width               4 # instruction decode B/W (insts/cycle)

-issue:width                4 # instruction issue B/W (insts/cycle)

-issue:inorder          false # run pipeline with in-order issue

-issue:wrongpath         true # issue instructions down wrong execution paths

-commit:width               4 # instruction commit B/W (insts/cycle)

-ruu:size                  16 # register update unit (RUU) size

-lsq:size                   8 # load/store queue (LSQ) size

-cache:dl1       dl1:128:32:4:l # l1 data cache config, i.e., {<config>|none}

-cache:dl1lat               1 # l1 data cache hit latency (in cycles)

-cache:dl2       ul2:1024:64:4:l # l2 data cache config, i.e., {<config>|none}

-cache:dl2lat               6 # l2 data cache hit latency (in cycles)

-cache:il1       il1:512:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2|none}

-cache:il1lat               1 # l1 instruction cache hit latency (in cycles)

-cache:il2                dl2 # l2 instruction cache config, i.e., {<config>|dl2|none}

-cache:il2lat               6 # l2 instruction cache hit latency (in cycles)

-cache:flush            false # flush caches on system calls

-cache:icompress        false # convert 64-bit inst addresses to 32-bit inst equivalents

-mem:lat         18 2 # memory access latency (<first_chunk> <inter_chunk>)

-mem:width                  8 # memory access bus width (in bytes)

-tlb:itlb        itlb:16:4096:4:l # instruction TLB config, i.e., {<config>|none}

-tlb:dtlb        dtlb:32:4096:4:l # data TLB config, i.e., {<config>|none}

-tlb:lat                   30 # inst/data TLB miss latency (in cycles)

-res:ialu                   4 # total number of integer ALU's available

-res:imult                  1 # total number of integer multiplier/dividers available

-res:memport                2 # total number of memory system ports available (to CPU)

-res:fpalu                  4 # total number of floating point ALU's available

-res:fpmult                 1 # total number of floating point multiplier/dividers available

# -pcstat              <null> # profile stat(s) against text addr's (mult uses ok)

-bugcompat              false # operate in backward-compatible bugs mode (for testing only)

  Pipetrace range arguments are formatted as follows:

    {{@|#}<start>}:{{@|#|+}<end>}

  Both ends of the range are optional, if neither are specified, the entire

  execution is traced.  Ranges that start with a `@' designate an address

  range to be traced, those that start with an `#' designate a cycle count

  range.  All other range values represent an instruction count range.  The

  second argument, if specified with a `+', indicates a value relative

  to the first argument, e.g., 1000:+100 == 1000:1100.  Program symbols may

  be used in all contexts.

    Examples:   -ptrace FOO.trc #0:#1000

                -ptrace BAR.trc @2000:

                -ptrace BLAH.trc :1500

                -ptrace UXXE.trc :

                -ptrace FOOBAR.trc @main:+278

  Branch predictor configuration examples for 2-level predictor:

    Configurations:   N, M, W, X

      N   # entries in first level (# of shift register(s))

      W   width of shift register(s)

      M   # entries in 2nd level (# of counters, or other FSM)

      X   (yes-1/no-0) xor history and address for 2nd level index

    Sample predictors:

      GAg     : 1, W, 2^W, 0

      GAp     : 1, W, M (M > 2^W), 0

      PAg     : N, W, 2^W, 0

      PAp     : N, W, M (M == 2^(N+W)), 0

      gshare  : 1, W, 2^W, 1

  Predictor `comb' combines a bimodal and a 2-level predictor.

  The cache config parameter <config> has the following format:

    <name>:<nsets>:<bsize>:<assoc>:<repl>

    <name>   - name of the cache being defined

    <nsets>  - number of sets in the cache

    <bsize>  - block size of the cache

    <assoc>  - associativity of the cache

    <repl>   - block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random

    Examples:   -cache:dl1 dl1:4096:32:1:l

                -dtlb dtlb:128:4096:32:r

  Cache levels can be unified by pointing a level of the instruction cache

  hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache

  configuration arguments.  Most sensible combinations are supported, e.g.,

    A unified l2 cache (il2 is pointed at dl2):

      -cache:il1 il1:128:64:1:l -cache:il2 dl2

      -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

    Or, a fully unified cache hierarchy (il1 pointed at dl1):

      -cache:il1 dl1

      -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting performance simulation **

sim: ** simulation statistics **

sim_num_insn                9998718 # total number of instructions committed

sim_num_refs                7324725 # total number of loads and stores committed

sim_num_loads               3564303 # total number of loads committed

sim_num_stores         3760422.0000 # total number of stores committed

sim_num_branches             496714 # total number of branches committed

sim_elapsed_time                 13 # total simulation time in seconds

sim_inst_rate           769132.1538 # simulation speed (in insts/sec)

sim_total_insn             10000001 # total number of instructions executed

sim_total_refs              7324988 # total number of loads and stores executed

sim_total_loads             3564455 # total number of loads executed

sim_total_stores       3760533.0000 # total number of stores executed

sim_total_branches           496900 # total number of branches executed

sim_cycle                  11667223 # total simulation time in cycles

sim_IPC                      0.8570 # instructions per cycle

sim_CPI                      1.1669 # cycles per instruction

sim_exec_BW                  0.8571 # total instructions (mis-spec + committed) per cycle

sim_IPB                     20.1297 # instruction per branch

IFQ_count                  46562985 # cumulative IFQ occupancy

IFQ_fcount                 11602984 # cumulative IFQ full count

ifq_occupancy                3.9909 # avg IFQ occupancy (insn's)

ifq_rate                     0.8571 # avg IFQ dispatch rate (insn/cycle)

ifq_latency                  4.6563 # avg IFQ occupant latency (cycle's)

ifq_full                     0.9945 # fraction of time (cycle's) IFQ was full

RUU_count                 103819235 # cumulative RUU occupancy

RUU_fcount                   592836 # cumulative RUU full count

ruu_occupancy                8.8984 # avg RUU occupancy (insn's)

ruu_rate                     0.8571 # avg RUU dispatch rate (insn/cycle)

ruu_latency                 10.3819 # avg RUU occupant latency (cycle's)

ruu_full                     0.0508 # fraction of time (cycle's) RUU was full

LSQ_count                  90636120 # cumulative LSQ occupancy

LSQ_fcount                 10192125 # cumulative LSQ full count

lsq_occupancy                7.7684 # avg LSQ occupancy (insn's)

lsq_rate                     0.8571 # avg LSQ dispatch rate (insn/cycle)

lsq_latency                  9.0636 # avg LSQ occupant latency (cycle's)

lsq_full                     0.8736 # fraction of time (cycle's) LSQ was full

bpred_bimod.lookups          496976 # total number of bpred lookups

bpred_bimod.updates          496713 # total number of updates

bpred_bimod.addr_hits        496383 # total number of address-predicted hits

bpred_bimod.dir_hits         496531 # total number of direction-predicted hits (includes addr-hits)

bpred_bimod.misses              182 # total number of misses

bpred_bimod.jr_hits             260 # total number of address-predicted hits for JR's

bpred_bimod.jr_seen             271 # total number of JR's seen

bpred_bimod.jr_non_ras_hits.PP            3 # total number of address-predicted hits for non-RAS JR's

bpred_bimod.jr_non_ras_seen.PP            6 # total number of non-RAS JR's seen

bpred_bimod.bpred_addr_rate    0.9993 # branch address-prediction rate (i.e., addr-hits/updates)

bpred_bimod.bpred_dir_rate    0.9996 # branch direction-prediction rate (i.e., all-hits/updates)

bpred_bimod.bpred_jr_rate    0.9594 # JR address-prediction rate (i.e., JR addr-hits/JRs seen)

bpred_bimod.bpred_jr_non_ras_rate.PP    0.5000 # non-RAS JR addr-pred rate (ie, non-RAS JR hits/JRs seen)

bpred_bimod.retstack_pushes          291 # total number of address pushed onto ret-addr stack

bpred_bimod.retstack_pops          281 # total number of address popped off of ret-addr stack

bpred_bimod.used_ras.PP          265 # total number of RAS predictions used

bpred_bimod.ras_hits.PP          257 # total number of RAS hits

bpred_bimod.ras_rate.PP    0.9698 # RAS prediction rate (i.e., RAS hits/used RAS)

il1.accesses               10000566 # total number of accesses

il1.hits                    9999950 # total number of hits

il1.misses                      616 # total number of misses

il1.replacements                237 # total number of replacements

il1.writebacks                    0 # total number of writebacks

il1.invalidations                 0 # total number of invalidations

il1.miss_rate                0.0001 # miss rate (i.e., misses/ref)

il1.repl_rate                0.0000 # replacement rate (i.e., repls/ref)

il1.wb_rate                  0.0000 # writeback rate (i.e., wrbks/ref)

il1.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)

dl1.accesses                7324754 # total number of accesses

dl1.hits                    6262067 # total number of hits

dl1.misses                  1062687 # total number of misses

dl1.replacements            1062175 # total number of replacements

dl1.writebacks               641812 # total number of writebacks

dl1.invalidations                 0 # total number of invalidations

dl1.miss_rate                0.1451 # miss rate (i.e., misses/ref)

dl1.repl_rate                0.1450 # replacement rate (i.e., repls/ref)

dl1.wb_rate                  0.0876 # writeback rate (i.e., wrbks/ref)

dl1.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)

ul2.accesses                1705115 # total number of accesses

ul2.hits                    1075115 # total number of hits

ul2.misses                   630000 # total number of misses

ul2.replacements             625904 # total number of replacements

ul2.writebacks               417340 # total number of writebacks

ul2.invalidations                 0 # total number of invalidations

ul2.miss_rate                0.3695 # miss rate (i.e., misses/ref)

ul2.repl_rate                0.3671 # replacement rate (i.e., repls/ref)

ul2.wb_rate                  0.2448 # writeback rate (i.e., wrbks/ref)

ul2.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)

itlb.accesses              10000566 # total number of accesses

itlb.hits                  10000551 # total number of hits

itlb.misses                      15 # total number of misses

itlb.replacements                 0 # total number of replacements

itlb.writebacks                   0 # total number of writebacks

itlb.invalidations                0 # total number of invalidations

itlb.miss_rate               0.0000 # miss rate (i.e., misses/ref)

itlb.repl_rate               0.0000 # replacement rate (i.e., repls/ref)

itlb.wb_rate                 0.0000 # writeback rate (i.e., wrbks/ref)

itlb.inv_rate                0.0000 # invalidation rate (i.e., invs/ref)

dtlb.accesses               7324771 # total number of accesses

dtlb.hits                   7268817 # total number of hits

dtlb.misses                   55954 # total number of misses

dtlb.replacements             55826 # total number of replacements

dtlb.writebacks                   0 # total number of writebacks

dtlb.invalidations                0 # total number of invalidations

dtlb.miss_rate               0.0076 # miss rate (i.e., misses/ref)

dtlb.repl_rate               0.0076 # replacement rate (i.e., repls/ref)

dtlb.wb_rate                 0.0000 # writeback rate (i.e., wrbks/ref)

dtlb.inv_rate                0.0000 # invalidation rate (i.e., invs/ref)

rename_power           1035812.9798 # total power usage of rename unit

bpred_power            13340565.8411 # total power usage of bpred unit

window_power           6038210.4799 # total power usage of instruction window

lsq_power              2353957.4117 # total power usage of load/store queue

regfile_power          8982703.9897 # total power usage of arch. regfile

icache_power           7830907.5780 # total power usage of icache

dcache_power           23281018.9904 # total power usage of dcache

dcache2_power          14364262.3853 # total power usage of dcache2

alu_power              56778997.7615 # total power usage of alu

falu_power             42809561.7962 # total power usage of falu

resultbus_power        5826522.5626 # total power usage of resultbus

clock_power            118071388.2580 # total power usage of clock

avg_rename_power             0.0888 # avg power usage of rename unit

avg_bpred_power              1.1434 # avg power usage of bpred unit

avg_window_power             0.5175 # avg power usage of instruction window

avg_lsq_power                0.2018 # avg power usage of lsq

avg_regfile_power            0.7699 # avg power usage of arch. regfile

avg_icache_power             0.6712 # avg power usage of icache

avg_dcache_power             1.9954 # avg power usage of dcache

avg_dcache2_power            1.2312 # avg power usage of dcache2

avg_alu_power                4.8665 # avg power usage of alu

avg_falu_power               3.6692 # avg power usage of falu

avg_resultbus_power          0.4994 # avg power usage of resultbus

avg_clock_power             10.1199 # avg power usage of clock

fetch_stage_power      21171473.4191 # total power usage of fetch stage

dispatch_stage_power   1035812.9798 # total power usage of dispatch stage

issue_stage_power      108642969.5914 # total power usage of issue stage

avg_fetch_power              1.8146 # average power of fetch unit per cycle

avg_dispatch_power           0.0888 # average power of dispatch unit per cycle

avg_issue_power              9.3118 # average power of issue unit per cycle

total_power            257904348.2380 # total power per cycle

avg_total_power_cycle       22.1050 # average total power per cycle

avg_total_power_cycle_nofp_nod2      17.2047 # average total power per cycle

avg_total_power_insn        25.7904 # average total power per insn

avg_total_power_insn_nofp_nod2      20.0731 # average total power per insn

rename_power_cc1        322969.7602 # total power usage of rename unit_cc1

bpred_power_cc1         567484.6120 # total power usage of bpred unit_cc1

window_power_cc1       2695058.8675 # total power usage of instruction window_cc1

lsq_power_cc1           566371.5895 # total power usage of lsq_cc1

regfile_power_cc1      2476550.9535 # total power usage of arch. regfile_cc1

icache_power_cc1       2442153.4392 # total power usage of icache_cc1

dcache_power_cc1       9380259.4845 # total power usage of dcache_cc1

dcache2_power_cc1      1309090.9086 # total power usage of dcache2_cc1

alu_power_cc1          4882348.4716 # total power usage of alu_cc1

resultbus_power_cc1    2221048.1326 # total power usage of resultbus_cc1

clock_power_cc1        29088334.1749 # total power usage of clock_cc1

avg_rename_power_cc1         0.0277 # avg power usage of rename unit_cc1

avg_bpred_power_cc1          0.0486 # avg power usage of bpred unit_cc1

avg_window_power_cc1         0.2310 # avg power usage of instruction window_cc1

avg_lsq_power_cc1            0.0485 # avg power usage of lsq_cc1

avg_regfile_power_cc1        0.2123 # avg power usage of arch. regfile_cc1

avg_icache_power_cc1         0.2093 # avg power usage of icache_cc1

avg_dcache_power_cc1         0.8040 # avg power usage of dcache_cc1

avg_dcache2_power_cc1        0.1122 # avg power usage of dcache2_cc1

avg_alu_power_cc1            0.4185 # avg power usage of alu_cc1

avg_resultbus_power_cc1       0.1904 # avg power usage of resultbus_cc1

avg_clock_power_cc1          2.4932 # avg power usage of clock_cc1

fetch_stage_power_cc1  3009638.0513 # total power usage of fetch stage_cc1

dispatch_stage_power_cc1  322969.7602 # total power usage of dispatch stage_cc1

issue_stage_power_cc1  21054177.4543 # total power usage of issue stage_cc1

avg_fetch_power_cc1          0.2580 # average power of fetch unit per cycle_cc1

avg_dispatch_power_cc1       0.0277 # average power of dispatch unit per cycle_cc1

avg_issue_power_cc1          1.8046 # average power of issue unit per cycle_cc1

total_power_cycle_cc1  55951670.3942 # total power per cycle_cc1

avg_total_power_cycle_cc1       4.7956 # average total power per cycle_cc1

avg_total_power_insn_cc1       5.5952 # average total power per insn_cc1

rename_power_cc2        221939.4193 # total power usage of rename unit_cc2

bpred_power_cc2         283976.4218 # total power usage of bpred unit_cc2

window_power_cc2       2183478.5414 # total power usage of instruction window_cc2

lsq_power_cc2           332709.0539 # total power usage of lsq_cc2

regfile_power_cc2       984989.2725 # total power usage of arch. regfile_cc2

icache_power_cc2       2442153.4392 # total power usage of icache_cc2

dcache_power_cc2       7307983.0981 # total power usage of dcache_cc2

dcache2_power_cc2      1049637.9156 # total power usage of dcache2_cc2

alu_power_cc2          2992850.4462 # total power usage of alu_cc2

resultbus_power_cc2    1618521.8857 # total power usage of resultbus_cc2

clock_power_cc2        20102892.6252 # total power usage of clock_cc2

avg_rename_power_cc2         0.0190 # avg power usage of rename unit_cc2

avg_bpred_power_cc2          0.0243 # avg power usage of bpred unit_cc2

avg_window_power_cc2         0.1871 # avg power usage of instruction window_cc2

avg_lsq_power_cc2            0.0285 # avg power usage of instruction lsq_cc2

avg_regfile_power_cc2        0.0844 # avg power usage of arch. regfile_cc2

avg_icache_power_cc2         0.2093 # avg power usage of icache_cc2

avg_dcache_power_cc2         0.6264 # avg power usage of dcache_cc2

avg_dcache2_power_cc2        0.0900 # avg power usage of dcache2_cc2

avg_alu_power_cc2            0.2565 # avg power usage of alu_cc2

avg_resultbus_power_cc2       0.1387 # avg power usage of resultbus_cc2

avg_clock_power_cc2          1.7230 # avg power usage of clock_cc2

fetch_stage_power_cc2  2726129.8610 # total power usage of fetch stage_cc2

dispatch_stage_power_cc2  221939.4193 # total power usage of dispatch stage_cc2

issue_stage_power_cc2  15485180.9409 # total power usage of issue stage_cc2

avg_fetch_power_cc2          0.2337 # average power of fetch unit per cycle_cc2

avg_dispatch_power_cc2       0.0190 # average power of dispatch unit per cycle_cc2

avg_issue_power_cc2          1.3272 # average power of issue unit per cycle_cc2

total_power_cycle_cc2  39521132.1188 # total power per cycle_cc2

avg_total_power_cycle_cc2       3.3874 # average total power per cycle_cc2

avg_total_power_insn_cc2       3.9521 # average total power per insn_cc2

rename_power_cc3        293223.7412 # total power usage of rename unit_cc3

bpred_power_cc3        1561288.9463 # total power usage of bpred unit_cc3

window_power_cc3       2512888.3723 # total power usage of instruction window_cc3

lsq_power_cc3           507823.2255 # total power usage of lsq_cc3

regfile_power_cc3      1601192.1431 # total power usage of arch. regfile_cc3

icache_power_cc3       2981028.8535 # total power usage of icache_cc3

dcache_power_cc3       8698101.1525 # total power usage of dcache_cc3

dcache2_power_cc3      2355155.9872 # total power usage of dcache2_cc3

alu_power_cc3          8182515.3756 # total power usage of alu_cc3

resultbus_power_cc3    1976825.7491 # total power usage of resultbus_cc3

clock_power_cc3        28948646.5377 # total power usage of clock_cc3

avg_rename_power_cc3         0.0251 # avg power usage of rename unit_cc3

avg_bpred_power_cc3          0.1338 # avg power usage of bpred unit_cc3

avg_window_power_cc3         0.2154 # avg power usage of instruction window_cc3

avg_lsq_power_cc3            0.0435 # avg power usage of instruction lsq_cc3

avg_regfile_power_cc3        0.1372 # avg power usage of arch. regfile_cc3

avg_icache_power_cc3         0.2555 # avg power usage of icache_cc3

avg_dcache_power_cc3         0.7455 # avg power usage of dcache_cc3

avg_dcache2_power_cc3        0.2019 # avg power usage of dcache2_cc3

avg_alu_power_cc3            0.7013 # avg power usage of alu_cc3

avg_resultbus_power_cc3       0.1694 # avg power usage of resultbus_cc3

avg_clock_power_cc3          2.4812 # avg power usage of clock_cc3

fetch_stage_power_cc3  4542317.7998 # total power usage of fetch stage_cc3

dispatch_stage_power_cc3  293223.7412 # total power usage of dispatch stage_cc3

issue_stage_power_cc3  24233309.8622 # total power usage of issue stage_cc3

avg_fetch_power_cc3          0.3893 # average power of fetch unit per cycle_cc3

avg_dispatch_power_cc3       0.0251 # average power of dispatch unit per cycle_cc3

avg_issue_power_cc3          2.0770 # average power of issue unit per cycle_cc3

total_power_cycle_cc3  59618690.0840 # total power per cycle_cc3

avg_total_power_cycle_cc3       5.1099 # average total power per cycle_cc3

avg_total_power_insn_cc3       5.9619 # average total power per insn_cc3

total_rename_access         9999553 # total number accesses of rename unit

total_bpred_access           496713 # total number accesses of bpred unit

total_window_access        43796129 # total number accesses of instruction window

total_lsq_access            7324796 # total number accesses of load/store queue

total_regfile_access       17532659 # total number accesses of arch. regfile

total_icache_access        10000985 # total number accesses of icache

total_dcache_access         7324754 # total number accesses of dcache

total_dcache2_access        1705115 # total number accesses of dcache2

total_alu_access            9998472 # total number accesses of alu

total_resultbus_access     13066581 # total number accesses of resultbus

avg_rename_access            0.8571 # avg number accesses of rename unit

avg_bpred_access             0.0426 # avg number accesses of bpred unit

avg_window_access            3.7538 # avg number accesses of instruction window

avg_lsq_access               0.6278 # avg number accesses of lsq

avg_regfile_access           1.5027 # avg number accesses of arch. regfile

avg_icache_access            0.8572 # avg number accesses of icache

avg_dcache_access            0.6278 # avg number accesses of dcache

avg_dcache2_access           0.1461 # avg number accesses of dcache2

avg_alu_access               0.8570 # avg number accesses of alu

avg_resultbus_access         1.1199 # avg number accesses of resultbus

max_rename_access                 4 # max number accesses of rename unit

max_bpred_access                  4 # max number accesses of bpred unit

max_window_access                15 # max number accesses of instruction window

max_lsq_access                    4 # max number accesses of load/store queue

max_regfile_access               11 # max number accesses of arch. regfile

max_icache_access                 4 # max number accesses of icache

max_dcache_access                 4 # max number accesses of dcache

max_dcache2_access                4 # max number accesses of dcache2

max_alu_access                    4 # max number accesses of alu

max_resultbus_access              7 # max number accesses of resultbus

max_cycle_power_cc1         12.7721 # maximum cycle power usage of cc1

max_cycle_power_cc2          9.7233 # maximum cycle power usage of cc2

max_cycle_power_cc3         10.7378 # maximum cycle power usage of cc3

parasitic_power_cc1    6787403.2765 # parasitic power cc1

parasitic_power_cc2    6787403.2765 # parasitic power cc2

parasitic_power_cc3    6787403.2765 # parasitic power cc3

min amperage                 0.0000 # min amperage

max amperage                 5.6515 # max amperage

slow_cycles                  0.0000 # slow cycles

fast_cycles                  0.0000 # fast cycles

sim_invalid_addrs                 0 # total non-speculative bogus addresses seen (debug var)

ld_text_base             0x00400000 # program text (code) segment base

ld_text_size                 147104 # program text (code) size in bytes

ld_data_base             0x10000000 # program initialized data segment base

ld_data_size                  91520 # program init'ed `.data' and uninit'ed `.bss' size in bytes

ld_stack_base            0x7fffc000 # program stack segment base (highest address in stack)

ld_stack_size                 16384 # program initial stack size

ld_prog_entry            0x00400140 # program entry point (initial PC)

ld_environ_base          0x7fff8000 # program environment base address address

ld_target_big_endian              0 # target executable endian-ness, non-zero if big endian

mem.page_count                49487 # total number of pages allocated

mem.page_mem                197948k # total size of memory pages allocated

mem.ptab_misses               56335 # total first level page table misses

mem.ptab_accesses          54160690 # total page table accesses

mem.ptab_miss_rate           0.0010 # first level page table miss rate

Cache Parameters:

  Size in bytes: 16384

  Number of sets: 512

  Associativity: 4

  Block Size (bytes): 8

Access Time: 9.27925e-09

Cycle Time:  1.09081e-08

Best Ndwl (L1): 8

Best Ndbl (L1): 1

Best Nspd (L1): 1

Best Ntwl (L1): 1

Best Ntbl (L1): 4

Best Ntspd (L1): 1

Time Components:

 data side (with Output driver) (ns): 8.44162

 tag side (ns): 8.55667

 decode_data (ns): 5.29318

 wordline_data (ns): 1.03507

 bitline_data (ns): 0.810785

 sense_amp_data (ns): 0.58

 decode_tag (ns): 2.37065

 wordline_tag (ns): 1.36749

 bitline_tag (ns): 0.158246

 sense_amp_tag (ns): 0.26

 compare (ns): 2.42991

 mux driver (ns): 1.6125

 sel inverter (ns): 0.357877

 data output driver (ns): 0.722579

 total data path (with output driver) (ns): 7.71904

 total tag path is set assoc (ns): 8.55667

 precharge time (ns): 1.6289

Cache Parameters:

  Size in bytes: 16384

  Number of sets: 512

  Associativity: 1

  Block Size (bytes): 32

Access Time: 6.07496e-09

Cycle Time:  7.99836e-09

Best Ndwl (L1): 2

Best Ndbl (L1): 2

Best Nspd (L1): 1

Best Ntwl (L1): 1

Best Ntbl (L1): 2

Best Ntspd (L1): 2

Time Components:

 data side (with Output driver) (ns): 6.07496

 tag side (ns): 6.05737

 decode_data (ns): 2.92313

 wordline_data (ns): 1.32956

 bitline_data (ns): 0.452976

 sense_amp_data (ns): 0.58

 decode_tag (ns): 1.84499

 wordline_tag (ns): 0.825016

 bitline_tag (ns): 0.252886

 sense_amp_tag (ns): 0.26

 compare (ns): 2.30022

 valid signal driver (ns): 0.574251

 data output driver (ns): 0.789293

 total data path (with output driver) (ns): 5.28567

 total tag path is dm (ns): 6.05737

 precharge time (ns): 1.92339

Cache Parameters:

  Size in bytes: 16384

  Number of sets: 128

  Associativity: 4

  Block Size (bytes): 32

Access Time: 9.14093e-09

Cycle Time:  1.11718e-08

Best Ndwl (L1): 4

Best Ndbl (L1): 2

Best Nspd (L1): 1

Best Ntwl (L1): 1

Best Ntbl (L1): 2

Best Ntspd (L1): 1

Time Components:

 data side (with Output driver) (ns): 6.05114

 tag side (ns): 7.98848

 decode_data (ns): 2.92572

 wordline_data (ns): 1.437

 bitline_data (ns): -0.0440331

 sense_amp_data (ns): 0.58

 decode_tag (ns): 1.46851

 wordline_tag (ns): 1.27791

 bitline_tag (ns): -0.0315811

 sense_amp_tag (ns): 0.26

 compare (ns): 2.29478

 mux driver (ns): 2.37376

 sel inverter (ns): 0.345094

 data output driver (ns): 1.15245

 total data path (with output driver) (ns): 4.89869

 total tag path is set assoc (ns): 7.98848

 precharge time (ns): 2.03083

Cache Parameters:

  Size in bytes: 262144

  Number of sets: 1024

  Associativity: 4

  Block Size (bytes): 64

Access Time: 1.44948e-08

Cycle Time:  1.76863e-08

Best Ndwl (L1): 2

Best Ndbl (L1): 2

Best Nspd (L1): 1

Best Ntwl (L1): 1

Best Ntbl (L1): 4

Best Ntspd (L1): 1

Time Components:

 data side (with Output driver) (ns): 11.3269

 tag side (ns): 12.2049

 decode_data (ns): 4.99158

 wordline_data (ns): 2.59771

 bitline_data (ns): 0.867749

 sense_amp_data (ns): 0.58

 decode_tag (ns): 4.52586

 wordline_tag (ns): 1.24192

 bitline_tag (ns): 0.46158

 sense_amp_tag (ns): 0.26

 compare (ns): 2.17054

 mux driver (ns): 3.21212

 sel inverter (ns): 0.332908

 data output driver (ns): 2.28987

 total data path (with output driver) (ns): 9.03704

 total tag path is set assoc (ns): 12.2049

 precharge time (ns): 3.19154