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sim-outorder_dvfs: SimpleScalar/PISA Tool Set version 3.0 of September, 1998.
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Copyright (c) 1994-1998 by Todd M. Austin.  All Rights Reserved.
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Processor Parameters:
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Issue Width: 4
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Window Size: 16
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Number of Virtual Registers: 32
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Number of Physical Registers: 16
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Datapath Width: 64
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Total Power Consumption: 24.105
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Branch Predictor Power Consumption: 1.14342  (5.17%)
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 branch target buffer power (W): 1.04097
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 local predict power (W): 0.0275244
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 global predict power (W): 0.031332
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 chooser power (W): 0.0206036
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 RAS power (W): 0.0229956
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Rename Logic Power Consumption: 0.0887797  (0.402%)
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 Instruction Decode Power (W): 0.0038821
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 RAT decode_power (W): 0.0273861
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 RAT wordline_power (W): 0.00645964
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 RAT bitline_power (W): 0.0486255
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 DCL Comparators (W): 0.0024263
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Instruction Window Power Consumption: 0.517536  (2.34%)
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 tagdrive (W): 0.0186418
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 tagmatch (W): 0.00697769
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 Selection Logic (W): 0.00331194
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 decode_power (W): 0.0131921
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 wordline_power (W): 0.0176803
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 bitline_power (W): 0.457732
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Load/Store Queue Power Consumption: 0.201758  (0.913%)
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 tagdrive (W): 0.0854673
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 tagmatch (W): 0.0207657
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 decode_power (W): 0.00194105
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 wordline_power (W): 0.00302882
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 bitline_power (W): 0.0905553
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Arch. Register File Power Consumption: 0.769909  (3.48%)
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 decode_power (W): 0.0273861
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 wordline_power (W): 0.0176803
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 bitline_power (W): 0.724843
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Result Bus Power Consumption: 0.499392  (2.26%)
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Total Clock Power: 10.1199  (45.8%)
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Int ALU Power: 1.19732  (5.42%)
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FP ALU Power: 3.66922  (16.6%)
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Instruction Cache Power Consumption: 0.614638  (2.78%)
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 decode_power (W): 0.186809
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 wordline_power (W): 0.00542611
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 bitline_power (W): 0.231588
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 senseamp_power (W): 0.07296
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 tagarray_power (W): 0.117856
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Itlb_power (W): 0.0565504 (0.256%)
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Data Cache Power Consumption: 1.80232  (8.15%)
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 decode_power (W): 0.15387
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 wordline_power (W): 0.0368784
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 bitline_power (W): 0.749615
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 senseamp_power (W): 0.58368
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 tagarray_power (W): 0.278274
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Dtlb_power (W): 0.193103 (0.874%)
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Level 2 Cache Power Consumption: 1.23116 (5.57%)
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 decode_power (W): 0.0990259
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 wordline_power (W): 0.00799512
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 bitline_power (W): 0.83087
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 senseamp_power (W): 0.14592
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 tagarray_power (W): 0.147353
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sim: command line: ./sim-outorder_dvfs -max:inst 60000000 mesa00.O2unroll.gcc.100M.ss -frames 1000 -meshfile mesa.in -ppmfile mesa.ppm 
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sim: simulation started @ Mon Nov 30 15:25:09 2009, options follow:
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sim-outorder: This simulator implements a very detailed out-of-order issue
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superscalar processor with a two-level memory system and speculative
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execution support.  This simulator is a performance simulator, tracking the
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latency of all pipeline operations.
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# -config                     # load configuration from a file
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# -dumpconfig                 # dump configuration to a file
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# -h                    false # print help message    
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# -v                    false # verbose operation     
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# -d                    false # enable debug message  
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# -i                    false # start in Dlite debugger
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-seed                       1 # random number generator seed (0 for timer seed)
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# -q                    false # initialize and terminate immediately
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# -chkpt               <null> # restore EIO trace execution from <fname>
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# -redir:sim           <null> # redirect simulator output to file (non-interactive only)
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# -redir:prog          <null> # redirect simulated program output to file
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-nice                       0 # simulator scheduling priority
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-max:inst            60000000 # maximum number of inst's to execute
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-fastfwd                    0 # number of insts skipped before timing starts
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# -ptrace              <null> # generate pipetrace, i.e., <fname|stdout|stderr> <range>
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-fetch:ifqsize              4 # instruction fetch queue size (in insts)
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-fetch:mplat                3 # extra branch mis-prediction latency
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-fetch:speed                1 # speed of front-end of machine relative to execution core
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-bpred                  bimod # branch predictor type {nottaken|taken|perfect|bimod|2lev|comb}
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-bpred:bimod     2048 # bimodal predictor config (<table size>)
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-bpred:2lev      1 1024 8 0 # 2-level predictor config (<l1size> <l2size> <hist_size> <xor>)
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-bpred:comb      1024 # combining predictor config (<meta_table_size>)
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-bpred:ras                  8 # return address stack size (0 for no return stack)
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-bpred:btb       512 4 # BTB config (<num_sets> <associativity>)
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# -bpred:spec_update       <null> # speculative predictors update in {ID|WB} (default non-spec)
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-decode:width               4 # instruction decode B/W (insts/cycle)
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-issue:width                4 # instruction issue B/W (insts/cycle)
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-issue:inorder          false # run pipeline with in-order issue
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-issue:wrongpath         true # issue instructions down wrong execution paths
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-commit:width               4 # instruction commit B/W (insts/cycle)
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-ruu:size                  16 # register update unit (RUU) size
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-lsq:size                   8 # load/store queue (LSQ) size
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-cache:dl1       dl1:128:32:4:l # l1 data cache config, i.e., {<config>|none}
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-cache:dl1lat               1 # l1 data cache hit latency (in cycles)
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-cache:dl2       ul2:1024:64:4:l # l2 data cache config, i.e., {<config>|none}
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-cache:dl2lat               6 # l2 data cache hit latency (in cycles)
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-cache:il1       il1:512:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2|none}
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-cache:il1lat               1 # l1 instruction cache hit latency (in cycles)
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-cache:il2                dl2 # l2 instruction cache config, i.e., {<config>|dl2|none}
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-cache:il2lat               6 # l2 instruction cache hit latency (in cycles)
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-cache:flush            false # flush caches on system calls
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-cache:icompress        false # convert 64-bit inst addresses to 32-bit inst equivalents
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-mem:lat         18 2 # memory access latency (<first_chunk> <inter_chunk>)
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-mem:width                  8 # memory access bus width (in bytes)
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-tlb:itlb        itlb:16:4096:4:l # instruction TLB config, i.e., {<config>|none}
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-tlb:dtlb        dtlb:32:4096:4:l # data TLB config, i.e., {<config>|none}
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-tlb:lat                   30 # inst/data TLB miss latency (in cycles)
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-res:ialu                   4 # total number of integer ALU's available
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-res:imult                  1 # total number of integer multiplier/dividers available
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-res:memport                2 # total number of memory system ports available (to CPU)
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-res:fpalu                  4 # total number of floating point ALU's available
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-res:fpmult                 1 # total number of floating point multiplier/dividers available
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# -pcstat              <null> # profile stat(s) against text addr's (mult uses ok)
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-bugcompat              false # operate in backward-compatible bugs mode (for testing only)
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  Pipetrace range arguments are formatted as follows:
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    {{@|#}<start>}:{{@|#|+}<end>}
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  Both ends of the range are optional, if neither are specified, the entire
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  execution is traced.  Ranges that start with a `@' designate an address
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  range to be traced, those that start with an `#' designate a cycle count
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  range.  All other range values represent an instruction count range.  The
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  second argument, if specified with a `+', indicates a value relative
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  to the first argument, e.g., 1000:+100 == 1000:1100.  Program symbols may
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  be used in all contexts.
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    Examples:   -ptrace FOO.trc #0:#1000
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                -ptrace BAR.trc @2000:
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                -ptrace BLAH.trc :1500
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                -ptrace UXXE.trc :
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                -ptrace FOOBAR.trc @main:+278
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  Branch predictor configuration examples for 2-level predictor:
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    Configurations:   N, M, W, X
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      N   # entries in first level (# of shift register(s))
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      W   width of shift register(s)
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      M   # entries in 2nd level (# of counters, or other FSM)
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      X   (yes-1/no-0) xor history and address for 2nd level index
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    Sample predictors:
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      GAg     : 1, W, 2^W, 0
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      GAp     : 1, W, M (M > 2^W), 0
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      PAg     : N, W, 2^W, 0
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      PAp     : N, W, M (M == 2^(N+W)), 0
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      gshare  : 1, W, 2^W, 1
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  Predictor `comb' combines a bimodal and a 2-level predictor.
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  The cache config parameter <config> has the following format:
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    <name>:<nsets>:<bsize>:<assoc>:<repl>
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    <name>   - name of the cache being defined
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    <nsets>  - number of sets in the cache
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    <bsize>  - block size of the cache
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    <assoc>  - associativity of the cache
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    <repl>   - block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random
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    Examples:   -cache:dl1 dl1:4096:32:1:l
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                -dtlb dtlb:128:4096:32:r
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  Cache levels can be unified by pointing a level of the instruction cache
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  hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache
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  configuration arguments.  Most sensible combinations are supported, e.g.,
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    A unified l2 cache (il2 is pointed at dl2):
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      -cache:il1 il1:128:64:1:l -cache:il2 dl2
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      -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
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    Or, a fully unified cache hierarchy (il1 pointed at dl1):
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      -cache:il1 dl1
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      -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
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sim: ** starting performance simulation **
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Cache Parameters:
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  Size in bytes: 16384
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  Number of sets: 512
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  Associativity: 4
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  Block Size (bytes): 8
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Access Time: 9.27925e-09
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Cycle Time:  1.09081e-08
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Best Ndwl (L1): 8
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Best Ndbl (L1): 1
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Best Nspd (L1): 1
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Best Ntwl (L1): 1
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Best Ntbl (L1): 4
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Best Ntspd (L1): 1
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Time Components:
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 data side (with Output driver) (ns): 8.44162
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 tag side (ns): 8.55667
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 decode_data (ns): 5.29318
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 wordline_data (ns): 1.03507
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 bitline_data (ns): 0.810785
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 sense_amp_data (ns): 0.58
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 decode_tag (ns): 2.37065
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 wordline_tag (ns): 1.36749
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 bitline_tag (ns): 0.158246
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 sense_amp_tag (ns): 0.26
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 compare (ns): 2.42991
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 mux driver (ns): 1.6125
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 sel inverter (ns): 0.357877
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 data output driver (ns): 0.722579
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 total data path (with output driver) (ns): 7.71904
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 total tag path is set assoc (ns): 8.55667
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 precharge time (ns): 1.6289
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Cache Parameters:
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  Size in bytes: 16384
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  Number of sets: 512
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  Associativity: 1
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  Block Size (bytes): 32
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Access Time: 6.07496e-09
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Cycle Time:  7.99836e-09
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Best Ndwl (L1): 2
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Best Ndbl (L1): 2
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Best Nspd (L1): 1
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Best Ntwl (L1): 1
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Best Ntbl (L1): 2
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Best Ntspd (L1): 2
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Time Components:
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 data side (with Output driver) (ns): 6.07496
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 tag side (ns): 6.05737
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 decode_data (ns): 2.92313
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 wordline_data (ns): 1.32956
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 bitline_data (ns): 0.452976
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 sense_amp_data (ns): 0.58
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 decode_tag (ns): 1.84499
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 wordline_tag (ns): 0.825016
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 bitline_tag (ns): 0.252886
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 sense_amp_tag (ns): 0.26
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 compare (ns): 2.30022
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 valid signal driver (ns): 0.574251
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 data output driver (ns): 0.789293
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 total data path (with output driver) (ns): 5.28567
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 total tag path is dm (ns): 6.05737
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 precharge time (ns): 1.92339
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Cache Parameters:
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  Size in bytes: 16384
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  Number of sets: 128
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  Associativity: 4
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  Block Size (bytes): 32
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Access Time: 9.14093e-09
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Cycle Time:  1.11718e-08
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Best Ndwl (L1): 4
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Best Ndbl (L1): 2
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Best Nspd (L1): 1
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Best Ntwl (L1): 1
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Best Ntbl (L1): 2
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Best Ntspd (L1): 1
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Time Components:
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 data side (with Output driver) (ns): 6.05114
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 tag side (ns): 7.98848
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 decode_data (ns): 2.92572
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 wordline_data (ns): 1.437
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 bitline_data (ns): -0.0440331
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 sense_amp_data (ns): 0.58
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 decode_tag (ns): 1.46851
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 wordline_tag (ns): 1.27791
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 bitline_tag (ns): -0.0315811
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 sense_amp_tag (ns): 0.26
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 compare (ns): 2.29478
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 mux driver (ns): 2.37376
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 sel inverter (ns): 0.345094
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 data output driver (ns): 1.15245
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 total data path (with output driver) (ns): 4.89869
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 total tag path is set assoc (ns): 7.98848
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 precharge time (ns): 2.03083
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Cache Parameters:
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  Size in bytes: 262144
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  Number of sets: 1024
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  Associativity: 4
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  Block Size (bytes): 64
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Access Time: 1.44948e-08
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Cycle Time:  1.76863e-08
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Best Ndwl (L1): 2
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Best Ndbl (L1): 2
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Best Nspd (L1): 1
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Best Ntwl (L1): 1
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Best Ntbl (L1): 4
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Best Ntspd (L1): 1
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Time Components:
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 data side (with Output driver) (ns): 11.3269
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 tag side (ns): 12.2049
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 decode_data (ns): 4.99158
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 wordline_data (ns): 2.59771
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 bitline_data (ns): 0.867749
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 sense_amp_data (ns): 0.58
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 decode_tag (ns): 4.52586
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 wordline_tag (ns): 1.24192
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 bitline_tag (ns): 0.46158
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 sense_amp_tag (ns): 0.26
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 compare (ns): 2.17054
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 mux driver (ns): 3.21212
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 sel inverter (ns): 0.332908
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 data output driver (ns): 2.28987
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 total data path (with output driver) (ns): 9.03704
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 total tag path is set assoc (ns): 12.2049
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 precharge time (ns): 3.19154
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Speed down!
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Cache Parameters:
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  Size in bytes: 16384
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  Number of sets: 512
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  Associativity: 4
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  Block Size (bytes): 8
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Access Time: 9.27925e-09
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Cycle Time:  1.09081e-08
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Best Ndwl (L1): 8
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Best Ndbl (L1): 1
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Best Nspd (L1): 1
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Best Ntwl (L1): 1
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Best Ntbl (L1): 4
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Best Ntspd (L1): 1
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Time Components:
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 data side (with Output driver) (ns): 8.44162
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 tag side (ns): 8.55667
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 decode_data (ns): 5.29318
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 wordline_data (ns): 1.03507
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 bitline_data (ns): 0.810785
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 sense_amp_data (ns): 0.58
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 decode_tag (ns): 2.37065
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 wordline_tag (ns): 1.36749
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 bitline_tag (ns): 0.158246
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 sense_amp_tag (ns): 0.26
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 compare (ns): 2.42991
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 mux driver (ns): 1.6125
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 sel inverter (ns): 0.357877
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 data output driver (ns): 0.722579
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 total data path (with output driver) (ns): 7.71904
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 total tag path is set assoc (ns): 8.55667
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 precharge time (ns): 1.6289
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Cache Parameters:
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  Size in bytes: 163
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Processor Parameters:
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Issue Width: 4
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Window Size: 16
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Number of Virtual Registers: 32
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Number of Physical Registers: 16
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Datapath Width: 64
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Total Power Consumption: 5.04786
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Branch Predictor Power Consumption: 0.163621  (5.37%)
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 branch target buffer power (W): 0.143672
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 local predict power (W): 0.00624411
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 global predict power (W): 0.00709918
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 chooser power (W): 0.00415536
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 RAS power (W): 0.00245052
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Rename Logic Power Consumption: 0.0104069  (0.341%)
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 Instruction Decode Power (W): 0.000485262
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 RAT decode_power (W): 0.00342327
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 RAT wordline_power (W): 0.000774826
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 RAT bitline_power (W): 0.00542029
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 DCL Comparators (W): 0.000303288
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Instruction Window Power Consumption: 0.0514899  (1.69%)
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 tagdrive (W): 0.00230958
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 tagmatch (W): 0.000872211
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 Selection Logic (W): 0.000413992
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 decode_power (W): 0.00164902
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 wordline_power (W): 0.00221003
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 bitline_power (W): 0.0440351
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Load/Store Queue Power Consumption: 0.0227073  (0.745%)
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 tagdrive (W): 0.0106829
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 tagmatch (W): 0.00259571
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 decode_power (W): 0.000242631
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 wordline_power (W): 0.000378602
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 bitline_power (W): 0.00880742
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Arch. Register File Power Consumption: 0.0805164  (2.64%)
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 decode_power (W): 0.00342327
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 wordline_power (W): 0.00221003
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 bitline_power (W): 0.0748831
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Result Bus Power Consumption: 0.0624241  (2.05%)
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Total Clock Power: 1.21766  (40%)
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Int ALU Power: 0.149665  (4.91%)
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FP ALU Power: 0.458652  (15%)
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Instruction Cache Power Consumption: 0.112954  (3.71%)
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 decode_power (W): 0.0233511
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 wordline_power (W): 0.000678263
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 bitline_power (W): 0.0289484
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 senseamp_power (W): 0.03648
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 tagarray_power (W): 0.0234957
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Itlb_power (W): 0.00879361 (0.289%)
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Data Cache Power Consumption: 0.46436  (15.2%)
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 decode_power (W): 0.0192338
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 wordline_power (W): 0.00460979
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 bitline_power (W): 0.0791131
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 senseamp_power (W): 0.29184
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 tagarray_power (W): 0.0695636
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Dtlb_power (W): 0.027654 (0.907%)
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Level 2 Cache Power Consumption: 0.216952 (7.12%)
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 decode_power (W): 0.0123782
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 wordline_power (W): 0.00099939
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 bitline_power (W): 0.103859
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 senseamp_power (W): 0.07296
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 tagarray_power (W): 0.0267553
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84
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  Number of sets: 512
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  Associativity: 1
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  Block Size (bytes): 32
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Access Time: 6.07496e-09
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Cycle Time:  7.99836e-09
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Best Ndwl (L1): 2
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Best Ndbl (L1): 2
437
Best Nspd (L1): 1
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Best Ntwl (L1): 1
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Best Ntbl (L1): 2
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Best Ntspd (L1): 2
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Time Components:
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 data side (with Output driver) (ns): 6.07496
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 tag side (ns): 6.05737
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 decode_data (ns): 2.92313
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 wordline_data (ns): 1.32956
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 bitline_data (ns): 0.452976
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 sense_amp_data (ns): 0.58
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 decode_tag (ns): 1.84499
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 wordline_tag (ns): 0.825016
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 bitline_tag (ns): 0.252886
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 sense_amp_tag (ns): 0.26
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 compare (ns): 2.30022
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 valid signal driver (ns): 0.574251
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 data output driver (ns): 0.789293
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 total data path (with output driver) (ns): 5.28567
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 total tag path is dm (ns): 6.05737
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 precharge time (ns): 1.92339
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Cache Parameters:
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  Size in bytes: 16384
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  Number of sets: 128
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  Associativity: 4
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  Block Size (bytes): 32
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Access Time: 9.14093e-09
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Cycle Time:  1.11718e-08
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Best Ndwl (L1): 4
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Best Ndbl (L1): 2
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Best Nspd (L1): 1
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Best Ntwl (L1): 1
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Best Ntbl (L1): 2
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Best Ntspd (L1): 1
475

    
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Time Components:
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 data side (with Output driver) (ns): 6.05114
478
 tag side (ns): 7.98848
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 decode_data (ns): 2.92572
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 wordline_data (ns): 1.437
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 bitline_data (ns): -0.0440331
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 sense_amp_data (ns): 0.58
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 decode_tag (ns): 1.46851
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 wordline_tag (ns): 1.27791
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 bitline_tag (ns): -0.0315811
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 sense_amp_tag (ns): 0.26
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 compare (ns): 2.29478
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 mux driver (ns): 2.37376
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 sel inverter (ns): 0.345094
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 data output driver (ns): 1.15245
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 total data path (with output driver) (ns): 4.89869
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 total tag path is set assoc (ns): 7.98848
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 precharge time (ns): 2.03083
494

    
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Cache Parameters:
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  Size in bytes: 262144
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  Number of sets: 1024
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  Associativity: 4
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  Block Size (bytes): 64
500

    
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Access Time: 1.44948e-08
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Cycle Time:  1.76863e-08
503

    
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Best Ndwl (L1): 2
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Best Ndbl (L1): 2
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Best Nspd (L1): 1
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Best Ntwl (L1): 1
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Best Ntbl (L1): 4
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Best Ntspd (L1): 1
510

    
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Time Components:
512
 data side (with Output driver) (ns): 11.3269
513
 tag side (ns): 12.2049
514
 decode_data (ns): 4.99158
515
 wordline_data (ns): 2.59771
516
 bitline_data (ns): 0.867749
517
 sense_amp_data (ns): 0.58
518
 decode_tag (ns): 4.52586
519
 wordline_tag (ns): 1.24192
520
 bitline_tag (ns): 0.46158
521
 sense_amp_tag (ns): 0.26
522
 compare (ns): 2.17054
523
 mux driver (ns): 3.21212
524
 sel inverter (ns): 0.332908
525
 data output driver (ns): 2.28987
526
 total data path (with output driver) (ns): 9.03704
527
 total tag path is set assoc (ns): 12.2049
528
 precharge time (ns): 3.19154
529
Speed up!
530

    
531
Cache Parameters:
532
  Size in bytes: 16384
533
  Number of sets: 512
534
  Associativity: 4
535
  Block Size (bytes): 8
536

    
537
Access Time: 9.27925e-09
538
Cycle Time:  1.09081e-08
539

    
540
Best Ndwl (L1): 8
541
Best Ndbl (L1): 1
542
Best Nspd (L1): 1
543
Best Ntwl (L1): 1
544
Best Ntbl (L1): 4
545
Best Ntspd (L1): 1
546

    
547
Time Components:
548
 data side (with Output driver) (ns): 8.44162
549
 tag side (ns): 8.55667
550
 decode_data (ns): 5.29318
551
 wordline_data (ns): 1.03507
552
 bitline_data (ns): 0.810785
553
 sense_amp_data (ns): 0.58
554
 decode_tag (ns): 2.37065
555
 wordline_tag (ns): 1.36749
556
 bitline_tag (ns): 0.158246
557
 sense_amp_tag (ns): 0.26
558
 compare (ns): 2.42991
559
 mux driver (ns): 1.6125
560
 sel inverter (ns): 0.357877
561
 data output driver (ns): 0.722579
562
 total data path (with output driver) (ns): 7.71904
563
 total tag path is set assoc (ns): 8.55667
564
 precharge time (ns): 1.6289
565

    
566
Cache Parameters:
567
  Size in bytes: 16384
568
  Number of sets: 512
569
  Associativity: 1
570
  Block Size (bytes): 32
571

    
572
Access Time: 6.07496e-09
573
Cycle Time:  7.99836e-09
574

    
575
Best Ndwl (L1): 2
576
Best Ndbl (L1): 2
577
Best Nspd (L1): 1
578
Best Ntwl (L1): 1
579
Best Ntbl (L1): 2
580
Best Ntspd (L1): 2
581

    
582
Time Components:
583
 data side (with Output driver) (ns): 6.07496
584
 tag side (ns): 6.05737
585
 decode_data (ns): 2.92313
586
 wordline_data (ns): 1.32956
587
 bitline_data (ns): 0.452976
588
 sense_amp_data (ns): 0.58
589
 decode_tag (ns): 1.84499
590
 wordline_tag (ns): 0.825016
591
 bitline_tag (ns): 0.252886
592
 sense_amp_tag (ns): 0.26
593
 compare (ns): 2.30022
594
 valid signal driver (ns): 0.574251
595
 data output driver (ns): 0.789293
596
 total data path (with output driver) (ns): 5.28567
597
 total tag path is dm (ns): 6.05737
598
 precharge time (ns): 1.92339
599

    
600
Cache Parameters:
601
  Size in bytes: 16384
602
  Number of sets: 128
603
  Associativity: 4
604
  Block Size (bytes
605
Processor Parameters:
606
Issue Width: 4
607
Window Size: 16
608
Number of Virtual Registers: 32
609
Number of Physical Registers: 16
610
Datapath Width: 64
611
Total Power Consumption: 24.105
612
Branch Predictor Power Consumption: 1.14342  (5.17%)
613
 branch target buffer power (W): 1.04097
614
 local predict power (W): 0.0275244
615
 global predict power (W): 0.031332
616
 chooser power (W): 0.0206036
617
 RAS power (W): 0.0229956
618
Rename Logic Power Consumption: 0.0887797  (0.402%)
619
 Instruction Decode Power (W): 0.0038821
620
 RAT decode_power (W): 0.0273861
621
 RAT wordline_power (W): 0.00645964
622
 RAT bitline_power (W): 0.0486255
623
 DCL Comparators (W): 0.0024263
624
Instruction Window Power Consumption: 0.517536  (2.34%)
625
 tagdrive (W): 0.0186418
626
 tagmatch (W): 0.00697769
627
 Selection Logic (W): 0.00331194
628
 decode_power (W): 0.0131921
629
 wordline_power (W): 0.0176803
630
 bitline_power (W): 0.457732
631
Load/Store Queue Power Consumption: 0.201758  (0.913%)
632
 tagdrive (W): 0.0854673
633
 tagmatch (W): 0.0207657
634
 decode_power (W): 0.00194105
635
 wordline_power (W): 0.00302882
636
 bitline_power (W): 0.0905553
637
Arch. Register File Power Consumption: 0.769909  (3.48%)
638
 decode_power (W): 0.0273861
639
 wordline_power (W): 0.0176803
640
 bitline_power (W): 0.724843
641
Result Bus Power Consumption: 0.499392  (2.26%)
642
Total Clock Power: 10.1199  (45.8%)
643
Int ALU Power: 1.19732  (5.42%)
644
FP ALU Power: 3.66922  (16.6%)
645
Instruction Cache Power Consumption: 0.614638  (2.78%)
646
 decode_power (W): 0.186809
647
 wordline_power (W): 0.00542611
648
 bitline_power (W): 0.231588
649
 senseamp_power (W): 0.07296
650
 tagarray_power (W): 0.117856
651
Itlb_power (W): 0.0565504 (0.256%)
652
Data Cache Power Consumption: 1.80232  (8.15%)
653
 decode_power (W): 0.15387
654
 wordline_power (W): 0.0368784
655
 bitline_power (W): 0.749615
656
 senseamp_power (W): 0.58368
657
 tagarray_power (W): 0.278274
658
Dtlb_power (W): 0.193103 (0.874%)
659
Level 2 Cache Power Consumption: 1.23116 (5.57%)
660
 decode_power (W): 0.0990259
661
 wordline_power (W): 0.00799512
662
 bitline_power (W): 0.83087
663
 senseamp_power (W): 0.14592
664
 tagarray_power (W): 0.147353
665
): 32
666

    
667
Access Time: 9.14093e-09
668
Cycle Time:  1.11718e-08
669

    
670
Best Ndwl (L1): 4
671
Best Ndbl (L1): 2
672
Best Nspd (L1): 1
673
Best Ntwl (L1): 1
674
Best Ntbl (L1): 2
675
Best Ntspd (L1): 1
676

    
677
Time Components:
678
 data side (with Output driver) (ns): 6.05114
679
 tag side (ns): 7.98848
680
 decode_data (ns): 2.92572
681
 wordline_data (ns): 1.437
682
 bitline_data (ns): -0.0440331
683
 sense_amp_data (ns): 0.58
684
 decode_tag (ns): 1.46851
685
 wordline_tag (ns): 1.27791
686
 bitline_tag (ns): -0.0315811
687
 sense_amp_tag (ns): 0.26
688
 compare (ns): 2.29478
689
 mux driver (ns): 2.37376
690
 sel inverter (ns): 0.345094
691
 data output driver (ns): 1.15245
692
 total data path (with output driver) (ns): 4.89869
693
 total tag path is set assoc (ns): 7.98848
694
 precharge time (ns): 2.03083
695

    
696
Cache Parameters:
697
  Size in bytes: 262144
698
  Number of sets: 1024
699
  Associativity: 4
700
  Block Size (bytes): 64
701

    
702
Access Time: 1.44948e-08
703
Cycle Time:  1.76863e-08
704

    
705
Best Ndwl (L1): 2
706
Best Ndbl (L1): 2
707
Best Nspd (L1): 1
708
Best Ntwl (L1): 1
709
Best Ntbl (L1): 4
710
Best Ntspd (L1): 1
711

    
712
Time Components:
713
 data side (with Output driver) (ns): 11.3269
714
 tag side (ns): 12.2049
715
 decode_data (ns): 4.99158
716
 wordline_data (ns): 2.59771
717
 bitline_data (ns): 0.867749
718
 sense_amp_data (ns): 0.58
719
 decode_tag (ns): 4.52586
720
 wordline_tag (ns): 1.24192
721
 bitline_tag (ns): 0.46158
722
 sense_amp_tag (ns): 0.26
723
 compare (ns): 2.17054
724
 mux driver (ns): 3.21212
725
 sel inverter (ns): 0.332908
726
 data output driver (ns): 2.28987
727
 total data path (with output driver) (ns): 9.03704
728
 total tag path is set assoc (ns): 12.2049
729
 precharge time (ns): 3.19154
730
Speed down!
731

    
732
Cache Parameters:
733
  Size in bytes: 16384
734
  Number of sets: 512
735
  Associativity: 4
736
  Block Size (bytes): 8
737

    
738
Access Time: 9.27925e-09
739
Cycle Time:  1.09081e-08
740

    
741
Best Ndwl (L1): 8
742
Best Ndbl (L1): 1
743
Best Nspd (L1): 1
744
Best Ntwl (L1): 1
745
Best Ntbl (L1): 4
746
Best Ntspd (L1): 1
747

    
748
Time Components:
749
 data side (with Output driver) (ns): 8.44162
750
 tag side (ns): 8.55667
751
 decode_data (ns): 5.29318
752
 wordline_data (ns): 1.03507
753
 bitline_data (ns): 0.810785
754
 sense_amp_data (ns): 0.58
755
 decode_tag (ns): 2.37065
756
 wordline_tag (ns): 1.36749
757
 bitline_tag (ns): 0.158246
758
 sense_amp_tag (ns): 0.26
759
 compare (ns): 2.42991
760
 mux driver (ns): 1.6125
761
 sel inverter (ns): 0.357877
762
 data output driver (ns): 0.722579
763
 total data path (with output driver) (ns): 7.71904
764
 total tag path is set assoc (ns): 8.55667
765
 precharge time (ns): 1.6289
766

    
767
Cache Parameters:
768
  Size in bytes: 16384
769
  Number of sets: 512
770
  Associativity: 1
771
  Block Size (bytes): 32
772

    
773
Access Time: 6.07496e-09
774
Cycle Time:  7.99836e-09
775

    
776
Best Ndwl (L1): 2
777
Best Ndbl (L1): 2
778
Best Nspd (L1): 1
779
Best Ntwl (L1): 1
780
Best Ntbl (L1): 2
781
Best Ntspd (L1): 2
782

    
783
Time Components:
784
 data side (with Output driver) (ns): 6.07496
785
 tag side (ns): 6.05737
786
 decode_data (ns): 2.92313
787
 wordline_data (ns): 1.32956
788
 bitline_data (ns): 0.452976
789
 sense_amp_data (ns): 0.58
790
 decode_tag (ns): 1.84499
791
 wordline_tag (ns): 0.825016
792
 bitline_tag (ns): 0.252886
793
 sense_amp_tag (ns): 0.26
794
 compare (ns): 2.30022
795
 valid signal driver (ns): 0.574251
796
 data output driver (ns): 0.789293
797
 total data path (with output driver) (ns): 5.28567
798
 total tag path is dm (ns): 6.05737
799
 precharge time (ns): 1.92339
800

    
801
Cache Parameters:
802
  Size in bytes: 16384
803
  Number of sets: 128
804
  Associativity: 4
805
  Block Size (bytes): 32
806

    
807
Access Time: 9.14093e-09
808
Cycle Time:  1.11718e-08
809

    
810
Best Ndwl (L1): 4
811
Best Ndbl (L1): 2
812
Best Nspd (L1): 1
813
Best Ntwl (L1): 1
814
Best Ntbl (L1): 2
815
Best Ntspd (L1): 1
816

    
817
Time Components:
818
 data side (with Output driver) (ns): 6.05114
819
 tag side (ns): 7.98848
820
 decode_data (ns): 2.92572
821
 wordline_data (ns): 1.437
822
 bitline_data (ns): -0.0440331
823
 sense_amp_data (ns): 0.58
824
 decode_tag (ns): 1.46851
825
 wordline_tag (ns): 1.27791
826
 bitline_tag (ns): -0.0315811
827
 sense_amp_tag (ns): 0.26
828
 compare (ns): 2.29478
829
 mux driver (ns): 2.37376
830
 sel inverter (ns): 0.345094
831
 data output driver (ns): 1.15245
832
 total data path (with output driver) (ns): 4.89869
833
 total tag path is set assoc (ns): 7.98848
834
 precharge time (ns): 2.03083
835

    
836
Cache Parameters:
837
  Size in bytes: 262144
838
  Number of sets: 1024
839
  Associativity: 4
840
  Block Size (bytes): 64
841

    
842
Access Time: 1.44948e-08
843
C
844
Processor Parameters:
845
Issue Width: 4
846
Window Size: 16
847
Number of Virtual Registers: 32
848
Number of Physical Registers: 16
849
Datapath Width: 64
850
Total Power Consumption: 5.04786
851
Branch Predictor Power Consumption: 0.163621  (5.37%)
852
 branch target buffer power (W): 0.143672
853
 local predict power (W): 0.00624411
854
 global predict power (W): 0.00709918
855
 chooser power (W): 0.00415536
856
 RAS power (W): 0.00245052
857
Rename Logic Power Consumption: 0.0104069  (0.341%)
858
 Instruction Decode Power (W): 0.000485262
859
 RAT decode_power (W): 0.00342327
860
 RAT wordline_power (W): 0.000774826
861
 RAT bitline_power (W): 0.00542029
862
 DCL Comparators (W): 0.000303288
863
Instruction Window Power Consumption: 0.0514899  (1.69%)
864
 tagdrive (W): 0.00230958
865
 tagmatch (W): 0.000872211
866
 Selection Logic (W): 0.000413992
867
 decode_power (W): 0.00164902
868
 wordline_power (W): 0.00221003
869
 bitline_power (W): 0.0440351
870
Load/Store Queue Power Consumption: 0.0227073  (0.745%)
871
 tagdrive (W): 0.0106829
872
 tagmatch (W): 0.00259571
873
 decode_power (W): 0.000242631
874
 wordline_power (W): 0.000378602
875
 bitline_power (W): 0.00880742
876
Arch. Register File Power Consumption: 0.0805164  (2.64%)
877
 decode_power (W): 0.00342327
878
 wordline_power (W): 0.00221003
879
 bitline_power (W): 0.0748831
880
Result Bus Power Consumption: 0.0624241  (2.05%)
881
Total Clock Power: 1.21766  (40%)
882
Int ALU Power: 0.149665  (4.91%)
883
FP ALU Power: 0.458652  (15%)
884
Instruction Cache Power Consumption: 0.112954  (3.71%)
885
 decode_power (W): 0.0233511
886
 wordline_power (W): 0.000678263
887
 bitline_power (W): 0.0289484
888
 senseamp_power (W): 0.03648
889
 tagarray_power (W): 0.0234957
890
Itlb_power (W): 0.00879361 (0.289%)
891
Data Cache Power Consumption: 0.46436  (15.2%)
892
 decode_power (W): 0.0192338
893
 wordline_power (W): 0.00460979
894
 bitline_power (W): 0.0791131
895
 senseamp_power (W): 0.29184
896
 tagarray_power (W): 0.0695636
897
Dtlb_power (W): 0.027654 (0.907%)
898
Level 2 Cache Power Consumption: 0.216952 (7.12%)
899
 decode_power (W): 0.0123782
900
 wordline_power (W): 0.00099939
901
 bitline_power (W): 0.103859
902
 senseamp_power (W): 0.07296
903
 tagarray_power (W): 0.0267553
904

    
905
sim: ** simulation statistics **
906
sim_num_insn               57067200 # total number of instructions committed
907
sim_num_refs               20811502 # total number of loads and stores committed
908
sim_num_loads              13617584 # total number of loads committed
909
sim_num_stores         7193918.0000 # total number of stores committed
910
sim_num_branches           10220174 # total number of branches committed
911
sim_elapsed_time                 54 # total simulation time in seconds
912
sim_inst_rate          1056800.0000 # simulation speed (in insts/sec)
913
sim_total_insn             60000000 # total number of instructions executed
914
sim_total_refs             21606834 # total number of loads and stores executed
915
sim_total_loads            14166005 # total number of loads executed
916
sim_total_stores       7440829.0000 # total number of stores executed
917
sim_total_branches         11040376 # total number of branches executed
918
sim_cycle                  41870396 # total simulation time in cycles
919
sim_IPC                      1.3629 # instructions per cycle
920
sim_CPI                      0.7337 # cycles per instruction
921
sim_exec_BW                  1.4330 # total instructions (mis-spec + committed) per cycle
922
sim_IPB                      5.5838 # instruction per branch
923
IFQ_count                 112786854 # cumulative IFQ occupancy
924
IFQ_fcount                 25285453 # cumulative IFQ full count
925
ifq_occupancy                2.6937 # avg IFQ occupancy (insn's)
926
ifq_rate                     1.4330 # avg IFQ dispatch rate (insn/cycle)
927
ifq_latency                  1.8798 # avg IFQ occupant latency (cycle's)
928
ifq_full                     0.6039 # fraction of time (cycle's) IFQ was full
929
RUU_count                 443780978 # cumulative RUU occupancy
930
RUU_fcount                 15228688 # cumulative RUU full count
931
ruu_occupancy               10.5989 # avg RUU occupancy (insn's)
932
ruu_rate                     1.4330 # avg RUU dispatch rate (insn/cycle)
933
ruu_latency                  7.3963 # avg RUU occupant latency (cycle's)
934
ruu_full                     0.3637 # fraction of time (cycle's) RUU was full
935
LSQ_count                 163980734 # cumulative LSQ occupancy
936
LSQ_fcount                  7136047 # cumulative LSQ full count
937
lsq_occupancy                3.9164 # avg LSQ occupancy (insn's)
938
lsq_rate                     1.4330 # avg LSQ dispatch rate (insn/cycle)
939
lsq_latency                  2.7330 # avg LSQ occupant latency (cycle's)
940
lsq_full                     0.1704 # fraction of time (cycle's) LSQ was full
941
bpred_bimod.lookups        11249516 # total number of bpred lookups
942
bpred_bimod.updates        10220173 # total number of updates
943
bpred_bimod.addr_hits       9929156 # total number of address-predicted hits
944
bpred_bimod.dir_hits        9929795 # total number of direction-predicted hits (includes addr-hits)
945
bpred_bimod.misses           290378 # total number of misses
946
bpred_bimod.jr_hits         1133262 # total number of address-predicted hits for JR's
947
bpred_bimod.jr_seen         1133309 # total number of JR's seen
948
bpred_bimod.jr_non_ras_hits.PP        30384 # total number of address-predicted hits for non-RAS JR's
949
bpred_bimod.jr_non_ras_seen.PP        30399 # total number of non-RAS JR's seen
950
bpred_bimod.bpred_addr_rate    0.9715 # branch address-prediction rate (i.e., addr-hits/updates)
951
bpred_bimod.bpred_dir_rate    0.9716 # branch direction-prediction rate (i.e., all-hits/updates)
952
bpred_bimod.bpred_jr_rate    1.0000 # JR address-prediction rate (i.e., JR addr-hits/JRs seen)
953
bpred_bimod.bpred_jr_non_ras_rate.PP    0.9995 # non-RAS JR addr-pred rate (ie, non-RAS JR hits/JRs seen)
954
bpred_bimod.retstack_pushes      1103626 # total number of address pushed onto ret-addr stack
955
bpred_bimod.retstack_pops      1102942 # total number of address popped off of ret-addr stack
956
bpred_bimod.used_ras.PP      1102910 # total number of RAS predictions used
957
bpred_bimod.ras_hits.PP      1102878 # total number of RAS hits
958
bpred_bimod.ras_rate.PP    1.0000 # RAS prediction rate (i.e., RAS hits/used RAS)
959
il1.accesses               62959164 # total number of accesses
960
il1.hits                   61121362 # total number of hits
961
il1.misses                  1837802 # total number of misses
962
il1.replacements            1837290 # total number of replacements
963
il1.writebacks                    0 # total number of writebacks
964
il1.invalidations                 0 # total number of invalidations
965
il1.miss_rate                0.0292 # miss rate (i.e., misses/ref)
966
il1.repl_rate                0.0292 # replacement rate (i.e., repls/ref)
967
il1.wb_rate                  0.0000 # writeback rate (i.e., wrbks/ref)
968
il1.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)
969
dl1.accesses               20609257 # total number of accesses
970
dl1.hits                   20556555 # total number of hits
971
dl1.misses                    52702 # total number of misses
972
dl1.replacements              52190 # total number of replacements
973
dl1.writebacks                49225 # total number of writebacks
974
dl1.invalidations                 0 # total number of invalidations
975
dl1.miss_rate                0.0026 # miss rate (i.e., misses/ref)
976
dl1.repl_rate                0.0025 # replacement rate (i.e., repls/ref)
977
dl1.wb_rate                  0.0024 # writeback rate (i.e., wrbks/ref)
978
dl1.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)
979
ul2.accesses                1939729 # total number of accesses
980
ul2.hits                    1913350 # total number of hits
981
ul2.misses                    26379 # total number of misses
982
ul2.replacements              22283 # total number of replacements
983
ul2.writebacks                21189 # total number of writebacks
984
ul2.invalidations                 0 # total number of invalidations
985
ul2.miss_rate                0.0136 # miss rate (i.e., misses/ref)
986
ul2.repl_rate                0.0115 # replacement rate (i.e., repls/ref)
987
ul2.wb_rate                  0.0109 # writeback rate (i.e., wrbks/ref)
988
ul2.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)
989
itlb.accesses              62959164 # total number of accesses
990
itlb.hits                  62959082 # total number of hits
991
itlb.misses                      82 # total number of misses
992
itlb.replacements                23 # total number of replacements
993
itlb.writebacks                   0 # total number of writebacks
994
itlb.invalidations                0 # total number of invalidations
995
itlb.miss_rate               0.0000 # miss rate (i.e., misses/ref)
996
itlb.repl_rate               0.0000 # replacement rate (i.e., repls/ref)
997
itlb.wb_rate                 0.0000 # writeback rate (i.e., wrbks/ref)
998
itlb.inv_rate                0.0000 # invalidation rate (i.e., invs/ref)
999
dtlb.accesses              21014664 # total number of accesses
1000
dtlb.hits                  21014246 # total number of hits
1001
dtlb.misses                     418 # total number of misses
1002
dtlb.replacements               290 # total number of replacements
1003
dtlb.writebacks                   0 # total number of writebacks
1004
dtlb.invalidations                0 # total number of invalidations
1005
dtlb.miss_rate               0.0000 # miss rate (i.e., misses/ref)
1006
dtlb.repl_rate               0.0000 # replacement rate (i.e., repls/ref)
1007
dtlb.wb_rate                 0.0000 # writeback rate (i.e., wrbks/ref)
1008
dtlb.inv_rate                0.0000 # invalidation rate (i.e., invs/ref)
1009
rename_power            447300.3710 # total power usage of rename unit
1010
bpred_power            6995379.8552 # total power usage of bpred unit
1011
window_power           2224632.6760 # total power usage of instruction window
1012
lsq_power               977168.7423 # total power usage of load/store queue
1013
regfile_power          3472924.0365 # total power usage of arch. regfile
1014
icache_power           5178630.2493 # total power usage of icache
1015
dcache_power           20822545.7602 # total power usage of dcache
1016
dcache2_power          9233426.4706 # total power usage of dcache2
1017
alu_power              26098475.8048 # total power usage of alu
1018
falu_power             19677422.2136 # total power usage of falu
1019
resultbus_power        2678162.0669 # total power usage of resultbus
1020
clock_power            52296762.5158 # total power usage of clock
1021
avg_rename_power             0.0107 # avg power usage of rename unit
1022
avg_bpred_power              0.1671 # avg power usage of bpred unit
1023
avg_window_power             0.0531 # avg power usage of instruction window
1024
avg_lsq_power                0.0233 # avg power usage of lsq
1025
avg_regfile_power            0.0829 # avg power usage of arch. regfile
1026
avg_icache_power             0.1237 # avg power usage of icache
1027
avg_dcache_power             0.4973 # avg power usage of dcache
1028
avg_dcache2_power            0.2205 # avg power usage of dcache2
1029
avg_alu_power                0.6233 # avg power usage of alu
1030
avg_falu_power               0.4700 # avg power usage of falu
1031
avg_resultbus_power          0.0640 # avg power usage of resultbus
1032
avg_clock_power              1.2490 # avg power usage of clock
1033
fetch_stage_power      12174010.1046 # total power usage of fetch stage
1034
dispatch_stage_power    447300.3710 # total power usage of dispatch stage
1035
issue_stage_power      62034411.5208 # total power usage of issue stage
1036
avg_fetch_power              0.2908 # average power of fetch unit per cycle
1037
avg_dispatch_power           0.0107 # average power of dispatch unit per cycle
1038
avg_issue_power              1.4816 # average power of issue unit per cycle
1039
total_power            130425408.5486 # total power per cycle
1040
avg_total_power_cycle        3.1150 # average total power per cycle
1041
avg_total_power_cycle_nofp_nod2       2.4245 # average total power per cycle
1042
avg_total_power_insn         2.1738 # average total power per insn
1043
avg_total_power_insn_nofp_nod2       1.6919 # average total power per insn
1044
rename_power_cc1        233790.8313 # total power usage of rename unit_cc1
1045
bpred_power_cc1        1297848.5562 # total power usage of bpred unit_cc1
1046
window_power_cc1       1730205.7838 # total power usage of instruction window_cc1
1047
lsq_power_cc1           173340.5818 # total power usage of lsq_cc1
1048
regfile_power_cc1      1922446.6122 # total power usage of arch. regfile_cc1
1049
icache_power_cc1       2913007.0910 # total power usage of icache_cc1
1050
dcache_power_cc1       6923311.8380 # total power usage of dcache_cc1
1051
dcache2_power_cc1       438764.7490 # total power usage of dcache2_cc1
1052
alu_power_cc1          6887038.2305 # total power usage of alu_cc1
1053
resultbus_power_cc1    1743242.9683 # total power usage of resultbus_cc1
1054
clock_power_cc1        18620378.8341 # total power usage of clock_cc1
1055
avg_rename_power_cc1         0.0056 # avg power usage of rename unit_cc1
1056
avg_bpred_power_cc1          0.0310 # avg power usage of bpred unit_cc1
1057
avg_window_power_cc1         0.0413 # avg power usage of instruction window_cc1
1058
avg_lsq_power_cc1            0.0041 # avg power usage of lsq_cc1
1059
avg_regfile_power_cc1        0.0459 # avg power usage of arch. regfile_cc1
1060
avg_icache_power_cc1         0.0696 # avg power usage of icache_cc1
1061
avg_dcache_power_cc1         0.1654 # avg power usage of dcache_cc1
1062
avg_dcache2_power_cc1        0.0105 # avg power usage of dcache2_cc1
1063
avg_alu_power_cc1            0.1645 # avg power usage of alu_cc1
1064
avg_resultbus_power_cc1       0.0416 # avg power usage of resultbus_cc1
1065
avg_clock_power_cc1          0.4447 # avg power usage of clock_cc1
1066
fetch_stage_power_cc1  4210855.6472 # total power usage of fetch stage_cc1
1067
dispatch_stage_power_cc1  233790.8313 # total power usage of dispatch stage_cc1
1068
issue_stage_power_cc1  17895904.1514 # total power usage of issue stage_cc1
1069
avg_fetch_power_cc1          0.1006 # average power of fetch unit per cycle_cc1
1070
avg_dispatch_power_cc1       0.0056 # average power of dispatch unit per cycle_cc1
1071
avg_issue_power_cc1          0.4274 # average power of issue unit per cycle_cc1
1072
total_power_cycle_cc1  42883376.0762 # total power per cycle_cc1
1073
avg_total_power_cycle_cc1       1.0242 # average total power per cycle_cc1
1074
avg_total_power_insn_cc1       0.7147 # average total power per insn_cc1
1075
rename_power_cc2        162686.5131 # total power usage of rename unit_cc2
1076
bpred_power_cc2         849972.6612 # total power usage of bpred unit_cc2
1077
window_power_cc2       1152791.0995 # total power usage of instruction window_cc2
1078
lsq_power_cc2           124598.9324 # total power usage of lsq_cc2
1079
regfile_power_cc2       518175.3480 # total power usage of arch. regfile_cc2
1080
icache_power_cc2       2913007.0910 # total power usage of icache_cc2
1081
dcache_power_cc2       5237616.5437 # total power usage of dcache_cc2
1082
dcache2_power_cc2       238588.5850 # total power usage of dcache2_cc2
1083
alu_power_cc2          2816449.1642 # total power usage of alu_cc2
1084
resultbus_power_cc2     969739.0117 # total power usage of resultbus_cc2
1085
clock_power_cc2        11919889.8009 # total power usage of clock_cc2
1086
avg_rename_power_cc2         0.0039 # avg power usage of rename unit_cc2
1087
avg_bpred_power_cc2          0.0203 # avg power usage of bpred unit_cc2
1088
avg_window_power_cc2         0.0275 # avg power usage of instruction window_cc2
1089
avg_lsq_power_cc2            0.0030 # avg power usage of instruction lsq_cc2
1090
avg_regfile_power_cc2        0.0124 # avg power usage of arch. regfile_cc2
1091
avg_icache_power_cc2         0.0696 # avg power usage of icache_cc2
1092
avg_dcache_power_cc2         0.1251 # avg power usage of dcache_cc2
1093
avg_dcache2_power_cc2        0.0057 # avg power usage of dcache2_cc2
1094
avg_alu_power_cc2            0.0673 # avg power usage of alu_cc2
1095
avg_resultbus_power_cc2       0.0232 # avg power usage of resultbus_cc2
1096
avg_clock_power_cc2          0.2847 # avg power usage of clock_cc2
1097
fetch_stage_power_cc2  3762979.7522 # total power usage of fetch stage_cc2
1098
dispatch_stage_power_cc2  162686.5131 # total power usage of dispatch stage_cc2
1099
issue_stage_power_cc2  10539783.3365 # total power usage of issue stage_cc2
1100
avg_fetch_power_cc2          0.0899 # average power of fetch unit per cycle_cc2
1101
avg_dispatch_power_cc2       0.0039 # average power of dispatch unit per cycle_cc2
1102
avg_issue_power_cc2          0.2517 # average power of issue unit per cycle_cc2
1103
total_power_cycle_cc2  26903514.7507 # total power per cycle_cc2
1104
avg_total_power_cycle_cc2       0.6425 # average total power per cycle_cc2
1105
avg_total_power_insn_cc2       0.4484 # average total power per insn_cc2
1106
rename_power_cc3        184037.4671 # total power usage of rename unit_cc3
1107
bpred_power_cc3        1422159.6884 # total power usage of bpred unit_cc3
1108
window_power_cc3       1192163.8501 # total power usage of instruction window_cc3
1109
lsq_power_cc3           203912.7395 # total power usage of lsq_cc3
1110
regfile_power_cc3       647293.8390 # total power usage of arch. regfile_cc3
1111
icache_power_cc3       3139569.4059 # total power usage of icache_cc3
1112
dcache_power_cc3       6641478.7321 # total power usage of dcache_cc3
1113
dcache2_power_cc3      1118056.1255 # total power usage of dcache2_cc3
1114
alu_power_cc3          4737592.9190 # total power usage of alu_cc3
1115
resultbus_power_cc3    1057436.2694 # total power usage of resultbus_cc3
1116
clock_power_cc3        15267202.2802 # total power usage of clock_cc3
1117
avg_rename_power_cc3         0.0044 # avg power usage of rename unit_cc3
1118
avg_bpred_power_cc3          0.0340 # avg power usage of bpred unit_cc3
1119
avg_window_power_cc3         0.0285 # avg power usage of instruction window_cc3
1120
avg_lsq_power_cc3            0.0049 # avg power usage of instruction lsq_cc3
1121
avg_regfile_power_cc3        0.0155 # avg power usage of arch. regfile_cc3
1122
avg_icache_power_cc3         0.0750 # avg power usage of icache_cc3
1123
avg_dcache_power_cc3         0.1586 # avg power usage of dcache_cc3
1124
avg_dcache2_power_cc3        0.0267 # avg power usage of dcache2_cc3
1125
avg_alu_power_cc3            0.1131 # avg power usage of alu_cc3
1126
avg_resultbus_power_cc3       0.0253 # avg power usage of resultbus_cc3
1127
avg_clock_power_cc3          0.3646 # avg power usage of clock_cc3
1128
fetch_stage_power_cc3  4561729.0943 # total power usage of fetch stage_cc3
1129
dispatch_stage_power_cc3  184037.4671 # total power usage of dispatch stage_cc3
1130
issue_stage_power_cc3  14950640.6356 # total power usage of issue stage_cc3
1131
avg_fetch_power_cc3          0.1089 # average power of fetch unit per cycle_cc3
1132
avg_dispatch_power_cc3       0.0044 # average power of dispatch unit per cycle_cc3
1133
avg_issue_power_cc3          0.3571 # average power of issue unit per cycle_cc3
1134
total_power_cycle_cc3  35610903.3162 # total power per cycle_cc3
1135
avg_total_power_cycle_cc3       0.8505 # average total power per cycle_cc3
1136
avg_total_power_insn_cc3       0.5935 # average total power per insn_cc3
1137
total_rename_access        59999073 # total number accesses of rename unit
1138
total_bpred_access         10220173 # total number accesses of bpred unit
1139
total_window_access       222916151 # total number accesses of instruction window
1140
total_lsq_access           21545778 # total number accesses of load/store queue
1141
total_regfile_access       83233066 # total number accesses of arch. regfile
1142
total_icache_access        62960159 # total number accesses of icache
1143
total_dcache_access        20609257 # total number accesses of dcache
1144
total_dcache2_access        1939729 # total number accesses of dcache2
1145
total_alu_access           56036354 # total number accesses of alu
1146
total_resultbus_access     61891382 # total number accesses of resultbus
1147
avg_rename_access            1.4330 # avg number accesses of rename unit
1148
avg_bpred_access             0.2441 # avg number accesses of bpred unit
1149
avg_window_access            5.3240 # avg number accesses of instruction window
1150
avg_lsq_access               0.5146 # avg number accesses of lsq
1151
avg_regfile_access           1.9879 # avg number accesses of arch. regfile
1152
avg_icache_access            1.5037 # avg number accesses of icache
1153
avg_dcache_access            0.4922 # avg number accesses of dcache
1154
avg_dcache2_access           0.0463 # avg number accesses of dcache2
1155
avg_alu_access               1.3383 # avg number accesses of alu
1156
avg_resultbus_access         1.4782 # avg number accesses of resultbus
1157
max_rename_access                 4 # max number accesses of rename unit
1158
max_bpred_access                  3 # max number accesses of bpred unit
1159
max_window_access                16 # max number accesses of instruction window
1160
max_lsq_access                    6 # max number accesses of load/store queue
1161
max_regfile_access               12 # max number accesses of arch. regfile
1162
max_icache_access                 4 # max number accesses of icache
1163
max_dcache_access                 4 # max number accesses of dcache
1164
max_dcache2_access                5 # max number accesses of dcache2
1165
max_alu_access                    4 # max number accesses of alu
1166
max_resultbus_access              7 # max number accesses of resultbus
1167
max_cycle_power_cc1         11.6230 # maximum cycle power usage of cc1
1168
max_cycle_power_cc2          8.8127 # maximum cycle power usage of cc2
1169
max_cycle_power_cc3          9.7900 # maximum cycle power usage of cc3
1170
parasitic_power_cc1    21052948.6906 # parasitic power cc1
1171
parasitic_power_cc2    21052948.6906 # parasitic power cc2
1172
parasitic_power_cc3    21052948.6906 # parasitic power cc3
1173
min amperage                 0.0000 # min amperage
1174
max amperage                 5.1526 # max amperage
1175
slow_cycles            41722921.0000 # slow cycles
1176
fast_cycles              97475.0000 # fast cycles
1177
sim_invalid_addrs                 0 # total non-speculative bogus addresses seen (debug var)
1178
ld_text_base             0x00400000 # program text (code) segment base
1179
ld_text_size                1288560 # program text (code) size in bytes
1180
ld_data_base             0x10000000 # program initialized data segment base
1181
ld_data_size                  39392 # program init'ed `.data' and uninit'ed `.bss' size in bytes
1182
ld_stack_base            0x7fffc000 # program stack segment base (highest address in stack)
1183
ld_stack_size                 16384 # program initial stack size
1184
ld_prog_entry            0x00400140 # program entry point (initial PC)
1185
ld_environ_base          0x7fff8000 # program environment base address address
1186
ld_target_big_endian              0 # target executable endian-ness, non-zero if big endian
1187
mem.page_count                  699 # total number of pages allocated
1188
mem.page_mem                  2796k # total size of memory pages allocated
1189
mem.ptab_misses                 707 # total first level page table misses
1190
mem.ptab_accesses         172542356 # total page table accesses
1191
mem.ptab_miss_rate           0.0000 # first level page table miss rate
1192

    
1193
ycle Time:  1.76863e-08
1194

    
1195
Best Ndwl (L1): 2
1196
Best Ndbl (L1): 2
1197
Best Nspd (L1): 1
1198
Best Ntwl (L1): 1
1199
Best Ntbl (L1): 4
1200
Best Ntspd (L1): 1
1201

    
1202
Time Components:
1203
 data side (with Output driver) (ns): 11.3269
1204
 tag side (ns): 12.2049
1205
 decode_data (ns): 4.99158
1206
 wordline_data (ns): 2.59771
1207
 bitline_data (ns): 0.867749
1208
 sense_amp_data (ns): 0.58
1209
 decode_tag (ns): 4.52586
1210
 wordline_tag (ns): 1.24192
1211
 bitline_tag (ns): 0.46158
1212
 sense_amp_tag (ns): 0.26
1213
 compare (ns): 2.17054
1214
 mux driver (ns): 3.21212
1215
 sel inverter (ns): 0.332908
1216
 data output driver (ns): 2.28987
1217
 total data path (with output driver) (ns): 9.03704
1218
 total tag path is set assoc (ns): 12.2049
1219
 precharge time (ns): 3.19154