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sim-outorder: SimpleScalar/PISA Tool Set version 3.0 of September, 1998.
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Copyright (c) 1994-1998 by Todd M. Austin.  All Rights Reserved.
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Processor Parameters:
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Issue Width: 4
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Window Size: 16
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Number of Virtual Registers: 32
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Number of Physical Registers: 16
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Datapath Width: 64
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Total Power Consumption: 24.105
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Branch Predictor Power Consumption: 1.14342  (5.17%)
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 branch target buffer power (W): 1.04097
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 local predict power (W): 0.0275244
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 global predict power (W): 0.031332
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 chooser power (W): 0.0206036
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 RAS power (W): 0.0229956
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Rename Logic Power Consumption: 0.0887797  (0.402%)
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 Instruction Decode Power (W): 0.0038821
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 RAT decode_power (W): 0.0273861
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 RAT wordline_power (W): 0.00645964
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 RAT bitline_power (W): 0.0486255
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 DCL Comparators (W): 0.0024263
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Instruction Window Power Consumption: 0.517536  (2.34%)
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 tagdrive (W): 0.0186418
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 tagmatch (W): 0.00697769
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 Selection Logic (W): 0.00331194
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 decode_power (W): 0.0131921
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 wordline_power (W): 0.0176803
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 bitline_power (W): 0.457732
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Load/Store Queue Power Consumption: 0.201758  (0.913%)
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 tagdrive (W): 0.0854673
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 tagmatch (W): 0.0207657
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 decode_power (W): 0.00194105
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 wordline_power (W): 0.00302882
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 bitline_power (W): 0.0905553
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Arch. Register File Power Consumption: 0.769909  (3.48%)
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 decode_power (W): 0.0273861
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 wordline_power (W): 0.0176803
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 bitline_power (W): 0.724843
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Result Bus Power Consumption: 0.499392  (2.26%)
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Total Clock Power: 10.1199  (45.8%)
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Int ALU Power: 1.19732  (5.42%)
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FP ALU Power: 3.66922  (16.6%)
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Instruction Cache Power Consumption: 0.614638  (2.78%)
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 decode_power (W): 0.186809
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 wordline_power (W): 0.00542611
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 bitline_power (W): 0.231588
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 senseamp_power (W): 0.07296
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 tagarray_power (W): 0.117856
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Itlb_power (W): 0.0565504 (0.256%)
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Data Cache Power Consumption: 1.80232  (8.15%)
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 decode_power (W): 0.15387
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 wordline_power (W): 0.0368784
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 bitline_power (W): 0.749615
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 senseamp_power (W): 0.58368
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 tagarray_power (W): 0.278274
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Dtlb_power (W): 0.193103 (0.874%)
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Level 2 Cache Power Consumption: 1.23116 (5.57%)
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 decode_power (W): 0.0990259
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 wordline_power (W): 0.00799512
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 bitline_power (W): 0.83087
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 senseamp_power (W): 0.14592
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 tagarray_power (W): 0.147353
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sim: command line: ./sim-outorder -max:inst 60000000 mcf00.O2unroll.gcc.100M.ss inp.in 
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sim: simulation started @ Mon Nov 30 14:55:14 2009, options follow:
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sim-outorder: This simulator implements a very detailed out-of-order issue
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superscalar processor with a two-level memory system and speculative
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execution support.  This simulator is a performance simulator, tracking the
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latency of all pipeline operations.
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# -config                     # load configuration from a file
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# -dumpconfig                 # dump configuration to a file
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# -h                    false # print help message    
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# -v                    false # verbose operation     
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# -d                    false # enable debug message  
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# -i                    false # start in Dlite debugger
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-seed                       1 # random number generator seed (0 for timer seed)
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# -q                    false # initialize and terminate immediately
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# -chkpt               <null> # restore EIO trace execution from <fname>
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# -redir:sim           <null> # redirect simulator output to file (non-interactive only)
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# -redir:prog          <null> # redirect simulated program output to file
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-nice                       0 # simulator scheduling priority
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-max:inst            60000000 # maximum number of inst's to execute
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-fastfwd                    0 # number of insts skipped before timing starts
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# -ptrace              <null> # generate pipetrace, i.e., <fname|stdout|stderr> <range>
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-fetch:ifqsize              4 # instruction fetch queue size (in insts)
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-fetch:mplat                3 # extra branch mis-prediction latency
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-fetch:speed                1 # speed of front-end of machine relative to execution core
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-bpred                  bimod # branch predictor type {nottaken|taken|perfect|bimod|2lev|comb}
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-bpred:bimod     2048 # bimodal predictor config (<table size>)
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-bpred:2lev      1 1024 8 0 # 2-level predictor config (<l1size> <l2size> <hist_size> <xor>)
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-bpred:comb      1024 # combining predictor config (<meta_table_size>)
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-bpred:ras                  8 # return address stack size (0 for no return stack)
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-bpred:btb       512 4 # BTB config (<num_sets> <associativity>)
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# -bpred:spec_update       <null> # speculative predictors update in {ID|WB} (default non-spec)
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-decode:width               4 # instruction decode B/W (insts/cycle)
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-issue:width                4 # instruction issue B/W (insts/cycle)
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-issue:inorder          false # run pipeline with in-order issue
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-issue:wrongpath         true # issue instructions down wrong execution paths
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-commit:width               4 # instruction commit B/W (insts/cycle)
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-ruu:size                  16 # register update unit (RUU) size
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-lsq:size                   8 # load/store queue (LSQ) size
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-cache:dl1       dl1:128:32:4:l # l1 data cache config, i.e., {<config>|none}
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-cache:dl1lat               1 # l1 data cache hit latency (in cycles)
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-cache:dl2       ul2:1024:64:4:l # l2 data cache config, i.e., {<config>|none}
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-cache:dl2lat               6 # l2 data cache hit latency (in cycles)
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-cache:il1       il1:512:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2|none}
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-cache:il1lat               1 # l1 instruction cache hit latency (in cycles)
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-cache:il2                dl2 # l2 instruction cache config, i.e., {<config>|dl2|none}
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-cache:il2lat               6 # l2 instruction cache hit latency (in cycles)
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-cache:flush            false # flush caches on system calls
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-cache:icompress        false # convert 64-bit inst addresses to 32-bit inst equivalents
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-mem:lat         18 2 # memory access latency (<first_chunk> <inter_chunk>)
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-mem:width                  8 # memory access bus width (in bytes)
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-tlb:itlb        itlb:16:4096:4:l # instruction TLB config, i.e., {<config>|none}
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-tlb:dtlb        dtlb:32:4096:4:l # data TLB config, i.e., {<config>|none}
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-tlb:lat                   30 # inst/data TLB miss latency (in cycles)
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-res:ialu                   4 # total number of integer ALU's available
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-res:imult                  1 # total number of integer multiplier/dividers available
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-res:memport                2 # total number of memory system ports available (to CPU)
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-res:fpalu                  4 # total number of floating point ALU's available
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-res:fpmult                 1 # total number of floating point multiplier/dividers available
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# -pcstat              <null> # profile stat(s) against text addr's (mult uses ok)
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-bugcompat              false # operate in backward-compatible bugs mode (for testing only)
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  Pipetrace range arguments are formatted as follows:
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    {{@|#}<start>}:{{@|#|+}<end>}
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  Both ends of the range are optional, if neither are specified, the entire
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  execution is traced.  Ranges that start with a `@' designate an address
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  range to be traced, those that start with an `#' designate a cycle count
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  range.  All other range values represent an instruction count range.  The
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  second argument, if specified with a `+', indicates a value relative
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  to the first argument, e.g., 1000:+100 == 1000:1100.  Program symbols may
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  be used in all contexts.
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    Examples:   -ptrace FOO.trc #0:#1000
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                -ptrace BAR.trc @2000:
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                -ptrace BLAH.trc :1500
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                -ptrace UXXE.trc :
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                -ptrace FOOBAR.trc @main:+278
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  Branch predictor configuration examples for 2-level predictor:
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    Configurations:   N, M, W, X
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      N   # entries in first level (# of shift register(s))
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      W   width of shift register(s)
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      M   # entries in 2nd level (# of counters, or other FSM)
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      X   (yes-1/no-0) xor history and address for 2nd level index
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    Sample predictors:
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      GAg     : 1, W, 2^W, 0
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      GAp     : 1, W, M (M > 2^W), 0
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      PAg     : N, W, 2^W, 0
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      PAp     : N, W, M (M == 2^(N+W)), 0
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      gshare  : 1, W, 2^W, 1
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  Predictor `comb' combines a bimodal and a 2-level predictor.
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  The cache config parameter <config> has the following format:
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    <name>:<nsets>:<bsize>:<assoc>:<repl>
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    <name>   - name of the cache being defined
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    <nsets>  - number of sets in the cache
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    <bsize>  - block size of the cache
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    <assoc>  - associativity of the cache
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    <repl>   - block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random
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    Examples:   -cache:dl1 dl1:4096:32:1:l
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                -dtlb dtlb:128:4096:32:r
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  Cache levels can be unified by pointing a level of the instruction cache
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  hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache
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  configuration arguments.  Most sensible combinations are supported, e.g.,
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    A unified l2 cache (il2 is pointed at dl2):
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      -cache:il1 il1:128:64:1:l -cache:il2 dl2
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      -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
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    Or, a fully unified cache hierarchy (il1 pointed at dl1):
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      -cache:il1 dl1
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      -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
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sim: ** starting performance simulation **
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sim: ** simulation statistics **
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sim_num_insn               57711408 # total number of instructions committed
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sim_num_refs               31304318 # total number of loads and stores committed
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sim_num_loads               3960187 # total number of loads committed
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sim_num_stores         27344131.0000 # total number of stores committed
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sim_num_branches            8103307 # total number of branches committed
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sim_elapsed_time                 46 # total simulation time in seconds
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sim_inst_rate          1254595.8261 # simulation speed (in insts/sec)
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sim_total_insn             60000002 # total number of instructions executed
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sim_total_refs             32011873 # total number of loads and stores executed
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sim_total_loads             4403645 # total number of loads executed
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sim_total_stores       27608228.0000 # total number of stores executed
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sim_total_branches          8532148 # total number of branches executed
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sim_cycle                  35015669 # total simulation time in cycles
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sim_IPC                      1.6482 # instructions per cycle
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sim_CPI                      0.6067 # cycles per instruction
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sim_exec_BW                  1.7135 # total instructions (mis-spec + committed) per cycle
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sim_IPB                      7.1220 # instruction per branch
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IFQ_count                  96049932 # cumulative IFQ occupancy
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IFQ_fcount                 22427178 # cumulative IFQ full count
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ifq_occupancy                2.7431 # avg IFQ occupancy (insn's)
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ifq_rate                     1.7135 # avg IFQ dispatch rate (insn/cycle)
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ifq_latency                  1.6008 # avg IFQ occupant latency (cycle's)
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ifq_full                     0.6405 # fraction of time (cycle's) IFQ was full
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RUU_count                 294028826 # cumulative RUU occupancy
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RUU_fcount                  2745943 # cumulative RUU full count
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ruu_occupancy                8.3971 # avg RUU occupancy (insn's)
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ruu_rate                     1.7135 # avg RUU dispatch rate (insn/cycle)
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ruu_latency                  4.9005 # avg RUU occupant latency (cycle's)
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ruu_full                     0.0784 # fraction of time (cycle's) RUU was full
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LSQ_count                 161462995 # cumulative LSQ occupancy
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LSQ_fcount                 14227833 # cumulative LSQ full count
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lsq_occupancy                4.6112 # avg LSQ occupancy (insn's)
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lsq_rate                     1.7135 # avg LSQ dispatch rate (insn/cycle)
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lsq_latency                  2.6910 # avg LSQ occupant latency (cycle's)
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lsq_full                     0.4063 # fraction of time (cycle's) LSQ was full
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bpred_bimod.lookups         8699834 # total number of bpred lookups
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bpred_bimod.updates         8103303 # total number of updates
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bpred_bimod.addr_hits       7883058 # total number of address-predicted hits
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bpred_bimod.dir_hits        7883312 # total number of direction-predicted hits (includes addr-hits)
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bpred_bimod.misses           219991 # total number of misses
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bpred_bimod.jr_hits          235052 # total number of address-predicted hits for JR's
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bpred_bimod.jr_seen          235068 # total number of JR's seen
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bpred_bimod.jr_non_ras_hits.PP        58690 # total number of address-predicted hits for non-RAS JR's
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bpred_bimod.jr_non_ras_seen.PP        58695 # total number of non-RAS JR's seen
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bpred_bimod.bpred_addr_rate    0.9728 # branch address-prediction rate (i.e., addr-hits/updates)
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bpred_bimod.bpred_dir_rate    0.9729 # branch direction-prediction rate (i.e., all-hits/updates)
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bpred_bimod.bpred_jr_rate    0.9999 # JR address-prediction rate (i.e., JR addr-hits/JRs seen)
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bpred_bimod.bpred_jr_non_ras_rate.PP    0.9999 # non-RAS JR addr-pred rate (ie, non-RAS JR hits/JRs seen)
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bpred_bimod.retstack_pushes       176617 # total number of address pushed onto ret-addr stack
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bpred_bimod.retstack_pops       205086 # total number of address popped off of ret-addr stack
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bpred_bimod.used_ras.PP       176373 # total number of RAS predictions used
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bpred_bimod.ras_hits.PP       176362 # total number of RAS hits
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bpred_bimod.ras_rate.PP    0.9999 # RAS prediction rate (i.e., RAS hits/used RAS)
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il1.accesses               62341180 # total number of accesses
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il1.hits                   60783880 # total number of hits
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il1.misses                  1557300 # total number of misses
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il1.replacements            1556876 # total number of replacements
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il1.writebacks                    0 # total number of writebacks
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il1.invalidations                 0 # total number of invalidations
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il1.miss_rate                0.0250 # miss rate (i.e., misses/ref)
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il1.repl_rate                0.0250 # replacement rate (i.e., repls/ref)
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il1.wb_rate                  0.0000 # writeback rate (i.e., wrbks/ref)
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il1.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)
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dl1.accesses               31502941 # total number of accesses
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dl1.hits                   28280475 # total number of hits
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dl1.misses                  3222466 # total number of misses
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dl1.replacements            3221954 # total number of replacements
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dl1.writebacks              3217608 # total number of writebacks
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dl1.invalidations                 0 # total number of invalidations
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dl1.miss_rate                0.1023 # miss rate (i.e., misses/ref)
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dl1.repl_rate                0.1023 # replacement rate (i.e., repls/ref)
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dl1.wb_rate                  0.1021 # writeback rate (i.e., wrbks/ref)
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dl1.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)
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ul2.accesses                7997374 # total number of accesses
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ul2.hits                    6385585 # total number of hits
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ul2.misses                  1611789 # total number of misses
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ul2.replacements            1607693 # total number of replacements
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ul2.writebacks              1606913 # total number of writebacks
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ul2.invalidations                 0 # total number of invalidations
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ul2.miss_rate                0.2015 # miss rate (i.e., misses/ref)
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ul2.repl_rate                0.2010 # replacement rate (i.e., repls/ref)
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ul2.wb_rate                  0.2009 # writeback rate (i.e., wrbks/ref)
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ul2.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)
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itlb.accesses              62341180 # total number of accesses
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itlb.hits                  62341160 # total number of hits
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itlb.misses                      20 # total number of misses
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itlb.replacements                 0 # total number of replacements
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itlb.writebacks                   0 # total number of writebacks
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itlb.invalidations                0 # total number of invalidations
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itlb.miss_rate               0.0000 # miss rate (i.e., misses/ref)
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itlb.repl_rate               0.0000 # replacement rate (i.e., repls/ref)
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itlb.wb_rate                 0.0000 # writeback rate (i.e., wrbks/ref)
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itlb.inv_rate                0.0000 # invalidation rate (i.e., invs/ref)
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dtlb.accesses              31547001 # total number of accesses
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dtlb.hits                  31521800 # total number of hits
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dtlb.misses                   25201 # total number of misses
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dtlb.replacements             25073 # total number of replacements
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dtlb.writebacks                   0 # total number of writebacks
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dtlb.invalidations                0 # total number of invalidations
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dtlb.miss_rate               0.0008 # miss rate (i.e., misses/ref)
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dtlb.repl_rate               0.0008 # replacement rate (i.e., repls/ref)
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dtlb.wb_rate                 0.0000 # writeback rate (i.e., wrbks/ref)
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dtlb.inv_rate                0.0000 # invalidation rate (i.e., invs/ref)
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rename_power           3108681.8561 # total power usage of rename unit
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bpred_power            40037705.4308 # total power usage of bpred unit
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window_power           18121876.9471 # total power usage of instruction window
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lsq_power              7064696.8520 # total power usage of load/store queue
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regfile_power          26958890.6792 # total power usage of arch. regfile
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icache_power           23502119.3883 # total power usage of icache
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dcache_power           69870992.8750 # total power usage of dcache
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dcache2_power          43110023.4753 # total power usage of dcache2
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alu_power              170405124.7978 # total power usage of alu
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falu_power             128480054.3431 # total power usage of falu
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resultbus_power        17486559.1719 # total power usage of resultbus
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clock_power            354355843.9179 # total power usage of clock
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avg_rename_power             0.0888 # avg power usage of rename unit
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avg_bpred_power              1.1434 # avg power usage of bpred unit
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avg_window_power             0.5175 # avg power usage of instruction window
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avg_lsq_power                0.2018 # avg power usage of lsq
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avg_regfile_power            0.7699 # avg power usage of arch. regfile
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avg_icache_power             0.6712 # avg power usage of icache
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avg_dcache_power             1.9954 # avg power usage of dcache
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avg_dcache2_power            1.2312 # avg power usage of dcache2
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avg_alu_power                4.8665 # avg power usage of alu
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avg_falu_power               3.6692 # avg power usage of falu
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avg_resultbus_power          0.4994 # avg power usage of resultbus
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avg_clock_power             10.1199 # avg power usage of clock
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fetch_stage_power      63539824.8191 # total power usage of fetch stage
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dispatch_stage_power   3108681.8561 # total power usage of dispatch stage
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issue_stage_power      326059274.1192 # total power usage of issue stage
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avg_fetch_power              1.8146 # average power of fetch unit per cycle
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avg_dispatch_power           0.0888 # average power of dispatch unit per cycle
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avg_issue_power              9.3118 # average power of issue unit per cycle
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total_power            774022515.3915 # total power per cycle
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avg_total_power_cycle       22.1050 # average total power per cycle
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avg_total_power_cycle_nofp_nod2      17.2047 # average total power per cycle
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avg_total_power_insn        12.9004 # average total power per insn
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avg_total_power_insn_nofp_nod2      10.0405 # average total power per insn
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rename_power_cc1       1856606.6757 # total power usage of rename unit_cc1
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bpred_power_cc1        7946811.2842 # total power usage of bpred unit_cc1
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window_power_cc1       14159399.8931 # total power usage of instruction window_cc1
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lsq_power_cc1          1494036.0010 # total power usage of lsq_cc1
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regfile_power_cc1      18504174.6107 # total power usage of arch. regfile_cc1
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icache_power_cc1       14854738.3286 # total power usage of icache_cc1
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dcache_power_cc1       34826045.6125 # total power usage of dcache_cc1
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dcache2_power_cc1      5884666.7802 # total power usage of dcache2_cc1
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alu_power_cc1          28064331.0043 # total power usage of alu_cc1
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resultbus_power_cc1    10794296.5882 # total power usage of resultbus_cc1
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clock_power_cc1        153390654.2164 # total power usage of clock_cc1
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avg_rename_power_cc1         0.0530 # avg power usage of rename unit_cc1
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avg_bpred_power_cc1          0.2270 # avg power usage of bpred unit_cc1
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avg_window_power_cc1         0.4044 # avg power usage of instruction window_cc1
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avg_lsq_power_cc1            0.0427 # avg power usage of lsq_cc1
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avg_regfile_power_cc1        0.5285 # avg power usage of arch. regfile_cc1
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avg_icache_power_cc1         0.4242 # avg power usage of icache_cc1
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avg_dcache_power_cc1         0.9946 # avg power usage of dcache_cc1
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avg_dcache2_power_cc1        0.1681 # avg power usage of dcache2_cc1
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avg_alu_power_cc1            0.8015 # avg power usage of alu_cc1
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avg_resultbus_power_cc1       0.3083 # avg power usage of resultbus_cc1
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avg_clock_power_cc1          4.3806 # avg power usage of clock_cc1
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fetch_stage_power_cc1  22801549.6128 # total power usage of fetch stage_cc1
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dispatch_stage_power_cc1 1856606.6757 # total power usage of dispatch stage_cc1
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issue_stage_power_cc1  95222775.8793 # total power usage of issue stage_cc1
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avg_fetch_power_cc1          0.6512 # average power of fetch unit per cycle_cc1
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avg_dispatch_power_cc1       0.0530 # average power of dispatch unit per cycle_cc1
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avg_issue_power_cc1          2.7194 # average power of issue unit per cycle_cc1
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total_power_cycle_cc1  291775760.9949 # total power per cycle_cc1
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avg_total_power_cycle_cc1       8.3327 # average total power per cycle_cc1
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avg_total_power_insn_cc1       4.8629 # average total power per insn_cc1
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rename_power_cc2       1331684.1902 # total power usage of rename unit_cc2
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bpred_power_cc2        4632749.6773 # total power usage of bpred unit_cc2
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window_power_cc2       10489756.7125 # total power usage of instruction window_cc2
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lsq_power_cc2          1245761.5747 # total power usage of lsq_cc2
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regfile_power_cc2      6116266.9388 # total power usage of arch. regfile_cc2
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icache_power_cc2       14854738.3286 # total power usage of icache_cc2
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dcache_power_cc2       31430811.2465 # total power usage of dcache_cc2
367
dcache2_power_cc2      4923038.6077 # total power usage of dcache2_cc2
368
alu_power_cc2          17370142.2447 # total power usage of alu_cc2
369
resultbus_power_cc2    6759172.0890 # total power usage of resultbus_cc2
370
clock_power_cc2        117210517.6241 # total power usage of clock_cc2
371
avg_rename_power_cc2         0.0380 # avg power usage of rename unit_cc2
372
avg_bpred_power_cc2          0.1323 # avg power usage of bpred unit_cc2
373
avg_window_power_cc2         0.2996 # avg power usage of instruction window_cc2
374
avg_lsq_power_cc2            0.0356 # avg power usage of instruction lsq_cc2
375
avg_regfile_power_cc2        0.1747 # avg power usage of arch. regfile_cc2
376
avg_icache_power_cc2         0.4242 # avg power usage of icache_cc2
377
avg_dcache_power_cc2         0.8976 # avg power usage of dcache_cc2
378
avg_dcache2_power_cc2        0.1406 # avg power usage of dcache2_cc2
379
avg_alu_power_cc2            0.4961 # avg power usage of alu_cc2
380
avg_resultbus_power_cc2       0.1930 # avg power usage of resultbus_cc2
381
avg_clock_power_cc2          3.3474 # avg power usage of clock_cc2
382
fetch_stage_power_cc2  19487488.0059 # total power usage of fetch stage_cc2
383
dispatch_stage_power_cc2 1331684.1902 # total power usage of dispatch stage_cc2
384
issue_stage_power_cc2  72218682.4751 # total power usage of issue stage_cc2
385
avg_fetch_power_cc2          0.5565 # average power of fetch unit per cycle_cc2
386
avg_dispatch_power_cc2       0.0380 # average power of dispatch unit per cycle_cc2
387
avg_issue_power_cc2          2.0625 # average power of issue unit per cycle_cc2
388
total_power_cycle_cc2  216364639.2341 # total power per cycle_cc2
389
avg_total_power_cycle_cc2       6.1791 # average total power per cycle_cc2
390
avg_total_power_insn_cc2       3.6061 # average total power per insn_cc2
391
rename_power_cc3       1456891.7076 # total power usage of rename unit_cc3
392
bpred_power_cc3        7846033.7928 # total power usage of bpred unit_cc3
393
window_power_cc3       10819689.6817 # total power usage of instruction window_cc3
394
lsq_power_cc3          1793584.2445 # total power usage of lsq_cc3
395
regfile_power_cc3      6756074.9205 # total power usage of arch. regfile_cc3
396
icache_power_cc3       15719476.4349 # total power usage of icache_cc3
397
dcache_power_cc3       34957085.4784 # total power usage of dcache_cc3
398
dcache2_power_cc3      8645575.3136 # total power usage of dcache2_cc3
399
alu_power_cc3          31604221.6075 # total power usage of alu_cc3
400
resultbus_power_cc3    7415662.4567 # total power usage of resultbus_cc3
401
clock_power_cc3        137020508.4685 # total power usage of clock_cc3
402
avg_rename_power_cc3         0.0416 # avg power usage of rename unit_cc3
403
avg_bpred_power_cc3          0.2241 # avg power usage of bpred unit_cc3
404
avg_window_power_cc3         0.3090 # avg power usage of instruction window_cc3
405
avg_lsq_power_cc3            0.0512 # avg power usage of instruction lsq_cc3
406
avg_regfile_power_cc3        0.1929 # avg power usage of arch. regfile_cc3
407
avg_icache_power_cc3         0.4489 # avg power usage of icache_cc3
408
avg_dcache_power_cc3         0.9983 # avg power usage of dcache_cc3
409
avg_dcache2_power_cc3        0.2469 # avg power usage of dcache2_cc3
410
avg_alu_power_cc3            0.9026 # avg power usage of alu_cc3
411
avg_resultbus_power_cc3       0.2118 # avg power usage of resultbus_cc3
412
avg_clock_power_cc3          3.9131 # avg power usage of clock_cc3
413
fetch_stage_power_cc3  23565510.2277 # total power usage of fetch stage_cc3
414
dispatch_stage_power_cc3 1456891.7076 # total power usage of dispatch stage_cc3
415
issue_stage_power_cc3  95235818.7823 # total power usage of issue stage_cc3
416
avg_fetch_power_cc3          0.6730 # average power of fetch unit per cycle_cc3
417
avg_dispatch_power_cc3       0.0416 # average power of dispatch unit per cycle_cc3
418
avg_issue_power_cc3          2.7198 # average power of issue unit per cycle_cc3
419
total_power_cycle_cc3  264034804.1067 # total power per cycle_cc3
420
avg_total_power_cycle_cc3       7.5405 # average total power per cycle_cc3
421
avg_total_power_insn_cc3       4.4006 # average total power per insn_cc3
422
total_rename_access        59999466 # total number accesses of rename unit
423
total_bpred_access          8103303 # total number accesses of bpred unit
424
total_window_access       208163106 # total number accesses of instruction window
425
total_lsq_access           31649814 # total number accesses of load/store queue
426
total_regfile_access      107455496 # total number accesses of arch. regfile
427
total_icache_access        62341747 # total number accesses of icache
428
total_dcache_access        31502941 # total number accesses of dcache
429
total_dcache2_access        7997374 # total number accesses of dcache2
430
total_alu_access           58029923 # total number accesses of alu
431
total_resultbus_access     54720508 # total number accesses of resultbus
432
avg_rename_access            1.7135 # avg number accesses of rename unit
433
avg_bpred_access             0.2314 # avg number accesses of bpred unit
434
avg_window_access            5.9449 # avg number accesses of instruction window
435
avg_lsq_access               0.9039 # avg number accesses of lsq
436
avg_regfile_access           3.0688 # avg number accesses of arch. regfile
437
avg_icache_access            1.7804 # avg number accesses of icache
438
avg_dcache_access            0.8997 # avg number accesses of dcache
439
avg_dcache2_access           0.2284 # avg number accesses of dcache2
440
avg_alu_access               1.6573 # avg number accesses of alu
441
avg_resultbus_access         1.5627 # avg number accesses of resultbus
442
max_rename_access                 4 # max number accesses of rename unit
443
max_bpred_access                  4 # max number accesses of bpred unit
444
max_window_access                16 # max number accesses of instruction window
445
max_lsq_access                    5 # max number accesses of load/store queue
446
max_regfile_access               11 # max number accesses of arch. regfile
447
max_icache_access                 4 # max number accesses of icache
448
max_dcache_access                 4 # max number accesses of dcache
449
max_dcache2_access                5 # max number accesses of dcache2
450
max_alu_access                    4 # max number accesses of alu
451
max_resultbus_access              6 # max number accesses of resultbus
452
max_cycle_power_cc1         12.9073 # maximum cycle power usage of cc1
453
max_cycle_power_cc2         10.0101 # maximum cycle power usage of cc2
454
max_cycle_power_cc3         11.0728 # maximum cycle power usage of cc3
455
parasitic_power_cc1    26667309.8784 # parasitic power cc1
456
parasitic_power_cc2    26667309.8784 # parasitic power cc2
457
parasitic_power_cc3    26667309.8784 # parasitic power cc3
458
min amperage                 0.0000 # min amperage
459
max amperage                 5.8278 # max amperage
460
slow_cycles                  0.0000 # slow cycles
461
fast_cycles                  0.0000 # fast cycles
462
sim_invalid_addrs                 0 # total non-speculative bogus addresses seen (debug var)
463
ld_text_base             0x00400000 # program text (code) segment base
464
ld_text_size                 121152 # program text (code) size in bytes
465
ld_data_base             0x10000000 # program initialized data segment base
466
ld_data_size                  19344 # program init'ed `.data' and uninit'ed `.bss' size in bytes
467
ld_stack_base            0x7fffc000 # program stack segment base (highest address in stack)
468
ld_stack_size                 16384 # program initial stack size
469
ld_prog_entry            0x00400140 # program entry point (initial PC)
470
ld_environ_base          0x7fff8000 # program environment base address address
471
ld_target_big_endian              0 # target executable endian-ness, non-zero if big endian
472
mem.page_count                24435 # total number of pages allocated
473
mem.page_mem                 97740k # total size of memory pages allocated
474
mem.ptab_misses               28132 # total first level page table misses
475
mem.ptab_accesses         188762081 # total page table accesses
476
mem.ptab_miss_rate           0.0001 # first level page table miss rate
477

    
478

    
479
Cache Parameters:
480
  Size in bytes: 16384
481
  Number of sets: 512
482
  Associativity: 4
483
  Block Size (bytes): 8
484

    
485
Access Time: 9.27925e-09
486
Cycle Time:  1.09081e-08
487

    
488
Best Ndwl (L1): 8
489
Best Ndbl (L1): 1
490
Best Nspd (L1): 1
491
Best Ntwl (L1): 1
492
Best Ntbl (L1): 4
493
Best Ntspd (L1): 1
494

    
495
Time Components:
496
 data side (with Output driver) (ns): 8.44162
497
 tag side (ns): 8.55667
498
 decode_data (ns): 5.29318
499
 wordline_data (ns): 1.03507
500
 bitline_data (ns): 0.810785
501
 sense_amp_data (ns): 0.58
502
 decode_tag (ns): 2.37065
503
 wordline_tag (ns): 1.36749
504
 bitline_tag (ns): 0.158246
505
 sense_amp_tag (ns): 0.26
506
 compare (ns): 2.42991
507
 mux driver (ns): 1.6125
508
 sel inverter (ns): 0.357877
509
 data output driver (ns): 0.722579
510
 total data path (with output driver) (ns): 7.71904
511
 total tag path is set assoc (ns): 8.55667
512
 precharge time (ns): 1.6289
513

    
514
Cache Parameters:
515
  Size in bytes: 16384
516
  Number of sets: 512
517
  Associativity: 1
518
  Block Size (bytes): 32
519

    
520
Access Time: 6.07496e-09
521
Cycle Time:  7.99836e-09
522

    
523
Best Ndwl (L1): 2
524
Best Ndbl (L1): 2
525
Best Nspd (L1): 1
526
Best Ntwl (L1): 1
527
Best Ntbl (L1): 2
528
Best Ntspd (L1): 2
529

    
530
Time Components:
531
 data side (with Output driver) (ns): 6.07496
532
 tag side (ns): 6.05737
533
 decode_data (ns): 2.92313
534
 wordline_data (ns): 1.32956
535
 bitline_data (ns): 0.452976
536
 sense_amp_data (ns): 0.58
537
 decode_tag (ns): 1.84499
538
 wordline_tag (ns): 0.825016
539
 bitline_tag (ns): 0.252886
540
 sense_amp_tag (ns): 0.26
541
 compare (ns): 2.30022
542
 valid signal driver (ns): 0.574251
543
 data output driver (ns): 0.789293
544
 total data path (with output driver) (ns): 5.28567
545
 total tag path is dm (ns): 6.05737
546
 precharge time (ns): 1.92339
547

    
548
Cache Parameters:
549
  Size in bytes: 16384
550
  Number of sets: 128
551
  Associativity: 4
552
  Block Size (bytes): 32
553

    
554
Access Time: 9.14093e-09
555
Cycle Time:  1.11718e-08
556

    
557
Best Ndwl (L1): 4
558
Best Ndbl (L1): 2
559
Best Nspd (L1): 1
560
Best Ntwl (L1): 1
561
Best Ntbl (L1): 2
562
Best Ntspd (L1): 1
563

    
564
Time Components:
565
 data side (with Output driver) (ns): 6.05114
566
 tag side (ns): 7.98848
567
 decode_data (ns): 2.92572
568
 wordline_data (ns): 1.437
569
 bitline_data (ns): -0.0440331
570
 sense_amp_data (ns): 0.58
571
 decode_tag (ns): 1.46851
572
 wordline_tag (ns): 1.27791
573
 bitline_tag (ns): -0.0315811
574
 sense_amp_tag (ns): 0.26
575
 compare (ns): 2.29478
576
 mux driver (ns): 2.37376
577
 sel inverter (ns): 0.345094
578
 data output driver (ns): 1.15245
579
 total data path (with output driver) (ns): 4.89869
580
 total tag path is set assoc (ns): 7.98848
581
 precharge time (ns): 2.03083
582

    
583
Cache Parameters:
584
  Size in bytes: 262144
585
  Number of sets: 1024
586
  Associativity: 4
587
  Block Size (bytes): 64
588

    
589
Access Time: 1.44948e-08
590
Cycle Time:  1.76863e-08
591

    
592
Best Ndwl (L1): 2
593
Best Ndbl (L1): 2
594
Best Nspd (L1): 1
595
Best Ntwl (L1): 1
596
Best Ntbl (L1): 4
597
Best Ntspd (L1): 1
598

    
599
Time Components:
600
 data side (with Output driver) (ns): 11.3269
601
 tag side (ns): 12.2049
602
 decode_data (ns): 4.99158
603
 wordline_data (ns): 2.59771
604
 bitline_data (ns): 0.867749
605
 sense_amp_data (ns): 0.58
606
 decode_tag (ns): 4.52586
607
 wordline_tag (ns): 1.24192
608
 bitline_tag (ns): 0.46158
609
 sense_amp_tag (ns): 0.26
610
 compare (ns): 2.17054
611
 mux driver (ns): 3.21212
612
 sel inverter (ns): 0.332908
613
 data output driver (ns): 2.28987
614
 total data path (with output driver) (ns): 9.03704
615
 total tag path is set assoc (ns): 12.2049
616
 precharge time (ns): 3.19154