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sim-outorder: SimpleScalar/PISA Tool Set version 3.0 of September, 1998.
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Copyright (c) 1994-1998 by Todd M. Austin.  All Rights Reserved.
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Processor Parameters:
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Issue Width: 4
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Window Size: 16
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Number of Virtual Registers: 32
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Number of Physical Registers: 16
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Datapath Width: 64
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Total Power Consumption: 24.105
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Branch Predictor Power Consumption: 1.14342  (5.17%)
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 branch target buffer power (W): 1.04097
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 local predict power (W): 0.0275244
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 global predict power (W): 0.031332
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 chooser power (W): 0.0206036
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 RAS power (W): 0.0229956
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Rename Logic Power Consumption: 0.0887797  (0.402%)
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 Instruction Decode Power (W): 0.0038821
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 RAT decode_power (W): 0.0273861
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 RAT wordline_power (W): 0.00645964
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 RAT bitline_power (W): 0.0486255
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 DCL Comparators (W): 0.0024263
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Instruction Window Power Consumption: 0.517536  (2.34%)
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 tagdrive (W): 0.0186418
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 tagmatch (W): 0.00697769
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 Selection Logic (W): 0.00331194
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 decode_power (W): 0.0131921
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 wordline_power (W): 0.0176803
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 bitline_power (W): 0.457732
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Load/Store Queue Power Consumption: 0.201758  (0.913%)
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 tagdrive (W): 0.0854673
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 tagmatch (W): 0.0207657
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 decode_power (W): 0.00194105
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 wordline_power (W): 0.00302882
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 bitline_power (W): 0.0905553
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Arch. Register File Power Consumption: 0.769909  (3.48%)
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 decode_power (W): 0.0273861
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 wordline_power (W): 0.0176803
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 bitline_power (W): 0.724843
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Result Bus Power Consumption: 0.499392  (2.26%)
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Total Clock Power: 10.1199  (45.8%)
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Int ALU Power: 1.19732  (5.42%)
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FP ALU Power: 3.66922  (16.6%)
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Instruction Cache Power Consumption: 0.614638  (2.78%)
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 decode_power (W): 0.186809
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 wordline_power (W): 0.00542611
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 bitline_power (W): 0.231588
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 senseamp_power (W): 0.07296
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 tagarray_power (W): 0.117856
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Itlb_power (W): 0.0565504 (0.256%)
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Data Cache Power Consumption: 1.80232  (8.15%)
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 decode_power (W): 0.15387
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 wordline_power (W): 0.0368784
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 bitline_power (W): 0.749615
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 senseamp_power (W): 0.58368
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 tagarray_power (W): 0.278274
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Dtlb_power (W): 0.193103 (0.874%)
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Level 2 Cache Power Consumption: 1.23116 (5.57%)
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 decode_power (W): 0.0990259
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 wordline_power (W): 0.00799512
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 bitline_power (W): 0.83087
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 senseamp_power (W): 0.14592
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 tagarray_power (W): 0.147353
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sim: command line: ./sim-outorder gzip00.O2unroll.gcc.100M.ss input.source 
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sim: simulation started @ Mon Nov 30 11:23:44 2009, options follow:
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sim-outorder: This simulator implements a very detailed out-of-order issue
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superscalar processor with a two-level memory system and speculative
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execution support.  This simulator is a performance simulator, tracking the
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latency of all pipeline operations.
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# -config                     # load configuration from a file
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# -dumpconfig                 # dump configuration to a file
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# -h                    false # print help message    
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# -v                    false # verbose operation     
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# -d                    false # enable debug message  
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# -i                    false # start in Dlite debugger
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-seed                       1 # random number generator seed (0 for timer seed)
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# -q                    false # initialize and terminate immediately
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# -chkpt               <null> # restore EIO trace execution from <fname>
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# -redir:sim           <null> # redirect simulator output to file (non-interactive only)
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# -redir:prog          <null> # redirect simulated program output to file
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-nice                       0 # simulator scheduling priority
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-max:inst                   0 # maximum number of inst's to execute
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-fastfwd                    0 # number of insts skipped before timing starts
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# -ptrace              <null> # generate pipetrace, i.e., <fname|stdout|stderr> <range>
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-fetch:ifqsize              4 # instruction fetch queue size (in insts)
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-fetch:mplat                3 # extra branch mis-prediction latency
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-fetch:speed                1 # speed of front-end of machine relative to execution core
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-bpred                  bimod # branch predictor type {nottaken|taken|perfect|bimod|2lev|comb}
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-bpred:bimod     2048 # bimodal predictor config (<table size>)
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-bpred:2lev      1 1024 8 0 # 2-level predictor config (<l1size> <l2size> <hist_size> <xor>)
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-bpred:comb      1024 # combining predictor config (<meta_table_size>)
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-bpred:ras                  8 # return address stack size (0 for no return stack)
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-bpred:btb       512 4 # BTB config (<num_sets> <associativity>)
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# -bpred:spec_update       <null> # speculative predictors update in {ID|WB} (default non-spec)
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-decode:width               4 # instruction decode B/W (insts/cycle)
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-issue:width                4 # instruction issue B/W (insts/cycle)
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-issue:inorder          false # run pipeline with in-order issue
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-issue:wrongpath         true # issue instructions down wrong execution paths
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-commit:width               4 # instruction commit B/W (insts/cycle)
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-ruu:size                  16 # register update unit (RUU) size
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-lsq:size                   8 # load/store queue (LSQ) size
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-cache:dl1       dl1:128:32:4:l # l1 data cache config, i.e., {<config>|none}
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-cache:dl1lat               1 # l1 data cache hit latency (in cycles)
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-cache:dl2       ul2:1024:64:4:l # l2 data cache config, i.e., {<config>|none}
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-cache:dl2lat               6 # l2 data cache hit latency (in cycles)
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-cache:il1       il1:512:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2|none}
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-cache:il1lat               1 # l1 instruction cache hit latency (in cycles)
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-cache:il2                dl2 # l2 instruction cache config, i.e., {<config>|dl2|none}
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-cache:il2lat               6 # l2 instruction cache hit latency (in cycles)
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-cache:flush            false # flush caches on system calls
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-cache:icompress        false # convert 64-bit inst addresses to 32-bit inst equivalents
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-mem:lat         18 2 # memory access latency (<first_chunk> <inter_chunk>)
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-mem:width                  8 # memory access bus width (in bytes)
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-tlb:itlb        itlb:16:4096:4:l # instruction TLB config, i.e., {<config>|none}
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-tlb:dtlb        dtlb:32:4096:4:l # data TLB config, i.e., {<config>|none}
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-tlb:lat                   30 # inst/data TLB miss latency (in cycles)
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-res:ialu                   4 # total number of integer ALU's available
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-res:imult                  1 # total number of integer multiplier/dividers available
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-res:memport                2 # total number of memory system ports available (to CPU)
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-res:fpalu                  4 # total number of floating point ALU's available
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-res:fpmult                 1 # total number of floating point multiplier/dividers available
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# -pcstat              <null> # profile stat(s) against text addr's (mult uses ok)
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-bugcompat              false # operate in backward-compatible bugs mode (for testing only)
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  Pipetrace range arguments are formatted as follows:
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    {{@|#}<start>}:{{@|#|+}<end>}
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  Both ends of the range are optional, if neither are specified, the entire
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  execution is traced.  Ranges that start with a `@' designate an address
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  range to be traced, those that start with an `#' designate a cycle count
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  range.  All other range values represent an instruction count range.  The
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  second argument, if specified with a `+', indicates a value relative
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  to the first argument, e.g., 1000:+100 == 1000:1100.  Program symbols may
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  be used in all contexts.
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    Examples:   -ptrace FOO.trc #0:#1000
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                -ptrace BAR.trc @2000:
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                -ptrace BLAH.trc :1500
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                -ptrace UXXE.trc :
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                -ptrace FOOBAR.trc @main:+278
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  Branch predictor configuration examples for 2-level predictor:
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    Configurations:   N, M, W, X
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      N   # entries in first level (# of shift register(s))
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      W   width of shift register(s)
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      M   # entries in 2nd level (# of counters, or other FSM)
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      X   (yes-1/no-0) xor history and address for 2nd level index
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    Sample predictors:
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      GAg     : 1, W, 2^W, 0
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      GAp     : 1, W, M (M > 2^W), 0
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      PAg     : N, W, 2^W, 0
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      PAp     : N, W, M (M == 2^(N+W)), 0
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      gshare  : 1, W, 2^W, 1
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  Predictor `comb' combines a bimodal and a 2-level predictor.
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  The cache config parameter <config> has the following format:
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    <name>:<nsets>:<bsize>:<assoc>:<repl>
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    <name>   - name of the cache being defined
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    <nsets>  - number of sets in the cache
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    <bsize>  - block size of the cache
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    <assoc>  - associativity of the cache
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    <repl>   - block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random
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    Examples:   -cache:dl1 dl1:4096:32:1:l
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                -dtlb dtlb:128:4096:32:r
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  Cache levels can be unified by pointing a level of the instruction cache
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  hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache
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  configuration arguments.  Most sensible combinations are supported, e.g.,
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    A unified l2 cache (il2 is pointed at dl2):
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      -cache:il1 il1:128:64:1:l -cache:il2 dl2
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      -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
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    Or, a fully unified cache hierarchy (il1 pointed at dl1):
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      -cache:il1 dl1
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      -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
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sim: ** starting performance simulation **
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spec_init
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Loading Input Data
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Duplicating 9553920 bytes
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Duplicating 19107840 bytes
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Duplicating 28893184 bytes
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Input data 67108864 bytes in length
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Compressing Input Data, level 1
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Compressed data 21267049 bytes in length
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Uncompressing Data
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Uncompressed data 67108864 bytes in length
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Uncompressed data compared correctly
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Compressing Input Data, level 3
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Compressed data 19456545 bytes in length
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Uncompressing Data
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Uncompressed data 67108864 bytes in length
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Uncompressed data compared correctly
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Compressing Input Data, level 5
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Compressed data 17614334 bytes in length
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Uncompressing Data
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Uncompressed data 67108864 bytes in length
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Uncompressed data compared correctly
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Compressing Input Data, level 7
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Compressed data 17251180 bytes in length
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Uncompressing Data
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Uncompressed data 67108864 bytes in length
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Uncompressed data compared correctly
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Compressing Input Data, level 9
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Compressed data 17212050 bytes in length
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Uncompressing Data
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Uncompressed data 67108864 bytes in length
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Uncompressed data compared correctly
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Tested 64MB buffer: OK!
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sim: ** simulation statistics **
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sim_num_insn            64370451696 # total number of instructions committed
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sim_num_refs            17416903471 # total number of loads and stores committed
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sim_num_loads           13125894168 # total number of loads committed
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sim_num_stores         4291009303.0000 # total number of stores committed
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sim_num_branches        12031113652 # total number of branches committed
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sim_elapsed_time              60670 # total simulation time in seconds
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sim_inst_rate          1060993.1053 # simulation speed (in insts/sec)
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sim_total_insn          72569295080 # total number of instructions executed
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sim_total_refs          19761348855 # total number of loads and stores executed
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sim_total_loads         14962903089 # total number of loads executed
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sim_total_stores       4798445766.0000 # total number of stores executed
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sim_total_branches      13596051264 # total number of branches executed
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sim_cycle               42212101867 # total simulation time in cycles
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sim_IPC                      1.5249 # instructions per cycle
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sim_CPI                      0.6558 # cycles per instruction
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sim_exec_BW                  1.7192 # total instructions (mis-spec + committed) per cycle
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sim_IPB                      5.3503 # instruction per branch
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IFQ_count              147570074716 # cumulative IFQ occupancy
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IFQ_fcount              34470031331 # cumulative IFQ full count
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ifq_occupancy                3.4959 # avg IFQ occupancy (insn's)
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ifq_rate                     1.7192 # avg IFQ dispatch rate (insn/cycle)
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ifq_latency                  2.0335 # avg IFQ occupant latency (cycle's)
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ifq_full                     0.8166 # fraction of time (cycle's) IFQ was full
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RUU_count              584966513777 # cumulative RUU occupancy
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RUU_fcount              27586361216 # cumulative RUU full count
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ruu_occupancy               13.8578 # avg RUU occupancy (insn's)
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ruu_rate                     1.7192 # avg RUU dispatch rate (insn/cycle)
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ruu_latency                  8.0608 # avg RUU occupant latency (cycle's)
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ruu_full                     0.6535 # fraction of time (cycle's) RUU was full
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LSQ_count              157161096198 # cumulative LSQ occupancy
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LSQ_fcount               3117301718 # cumulative LSQ full count
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lsq_occupancy                3.7231 # avg LSQ occupancy (insn's)
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lsq_rate                     1.7192 # avg LSQ dispatch rate (insn/cycle)
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lsq_latency                  2.1657 # avg LSQ occupant latency (cycle's)
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lsq_full                     0.0738 # fraction of time (cycle's) LSQ was full
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bpred_bimod.lookups     14148051604 # total number of bpred lookups
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bpred_bimod.updates     12031113652 # total number of updates
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bpred_bimod.addr_hits   11262876015 # total number of address-predicted hits
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bpred_bimod.dir_hits    11267091760 # total number of direction-predicted hits (includes addr-hits)
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bpred_bimod.misses        764021892 # total number of misses
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bpred_bimod.jr_hits       266070508 # total number of address-predicted hits for JR's
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bpred_bimod.jr_seen       270318863 # total number of JR's seen
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bpred_bimod.jr_non_ras_hits.PP       223687 # total number of address-predicted hits for non-RAS JR's
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bpred_bimod.jr_non_ras_seen.PP      1027630 # total number of non-RAS JR's seen
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bpred_bimod.bpred_addr_rate    0.9361 # branch address-prediction rate (i.e., addr-hits/updates)
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bpred_bimod.bpred_dir_rate    0.9365 # branch direction-prediction rate (i.e., all-hits/updates)
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bpred_bimod.bpred_jr_rate    0.9843 # JR address-prediction rate (i.e., JR addr-hits/JRs seen)
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bpred_bimod.bpred_jr_non_ras_rate.PP    0.2177 # non-RAS JR addr-pred rate (ie, non-RAS JR hits/JRs seen)
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bpred_bimod.retstack_pushes    351039727 # total number of address pushed onto ret-addr stack
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bpred_bimod.retstack_pops    326647030 # total number of address popped off of ret-addr stack
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bpred_bimod.used_ras.PP    269291233 # total number of RAS predictions used
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bpred_bimod.ras_hits.PP    265846821 # total number of RAS hits
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bpred_bimod.ras_rate.PP    0.9872 # RAS prediction rate (i.e., RAS hits/used RAS)
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il1.accesses            75366103087 # total number of accesses
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il1.hits                75335279379 # total number of hits
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il1.misses                 30823708 # total number of misses
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il1.replacements           30823196 # total number of replacements
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il1.writebacks                    0 # total number of writebacks
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il1.invalidations                 0 # total number of invalidations
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il1.miss_rate                0.0004 # miss rate (i.e., misses/ref)
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il1.repl_rate                0.0004 # replacement rate (i.e., repls/ref)
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il1.wb_rate                  0.0000 # writeback rate (i.e., wrbks/ref)
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il1.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)
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dl1.accesses            17702251238 # total number of accesses
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dl1.hits                15204413658 # total number of hits
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dl1.misses               2497837580 # total number of misses
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dl1.replacements         2497837068 # total number of replacements
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dl1.writebacks            329872927 # total number of writebacks
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dl1.invalidations                 0 # total number of invalidations
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dl1.miss_rate                0.1411 # miss rate (i.e., misses/ref)
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dl1.repl_rate                0.1411 # replacement rate (i.e., repls/ref)
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dl1.wb_rate                  0.0186 # writeback rate (i.e., wrbks/ref)
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dl1.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)
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ul2.accesses             2858534215 # total number of accesses
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ul2.hits                 2826262238 # total number of hits
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ul2.misses                 32271977 # total number of misses
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ul2.replacements           32267881 # total number of replacements
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ul2.writebacks             21507246 # total number of writebacks
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ul2.invalidations                 0 # total number of invalidations
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ul2.miss_rate                0.0113 # miss rate (i.e., misses/ref)
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ul2.repl_rate                0.0113 # replacement rate (i.e., repls/ref)
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ul2.wb_rate                  0.0075 # writeback rate (i.e., wrbks/ref)
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ul2.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)
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itlb.accesses           75366103087 # total number of accesses
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itlb.hits               75366103047 # total number of hits
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itlb.misses                      40 # total number of misses
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itlb.replacements                 0 # total number of replacements
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itlb.writebacks                   0 # total number of writebacks
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itlb.invalidations                0 # total number of invalidations
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itlb.miss_rate               0.0000 # miss rate (i.e., misses/ref)
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itlb.repl_rate               0.0000 # replacement rate (i.e., repls/ref)
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itlb.wb_rate                 0.0000 # writeback rate (i.e., wrbks/ref)
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itlb.inv_rate                0.0000 # invalidation rate (i.e., invs/ref)
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dtlb.accesses           18112737968 # total number of accesses
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dtlb.hits               18112231998 # total number of hits
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dtlb.misses                  505970 # total number of misses
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dtlb.replacements            505842 # total number of replacements
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dtlb.writebacks                   0 # total number of writebacks
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dtlb.invalidations                0 # total number of invalidations
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dtlb.miss_rate               0.0000 # miss rate (i.e., misses/ref)
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dtlb.repl_rate               0.0000 # replacement rate (i.e., repls/ref)
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dtlb.wb_rate                 0.0000 # writeback rate (i.e., wrbks/ref)
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dtlb.inv_rate                0.0000 # invalidation rate (i.e., invs/ref)
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rename_power           3747581864.9569 # total power usage of rename unit
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bpred_power            48266280687.2328 # total power usage of bpred unit
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window_power           21846289307.4522 # total power usage of instruction window
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lsq_power              8516642958.0262 # total power usage of load/store queue
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regfile_power          32499475754.2160 # total power usage of arch. regfile
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icache_power           28332273525.6432 # total power usage of icache
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dcache_power           84230956463.0284 # total power usage of dcache
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dcache2_power          51969985281.0791 # total power usage of dcache2
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alu_power              205427054474.2720 # total power usage of alu
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falu_power             154885379974.6880 # total power usage of falu
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resultbus_power        21080398281.4192 # total power usage of resultbus
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clock_power            427183493471.9036 # total power usage of clock
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avg_rename_power             0.0888 # avg power usage of rename unit
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avg_bpred_power              1.1434 # avg power usage of bpred unit
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avg_window_power             0.5175 # avg power usage of instruction window
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avg_lsq_power                0.2018 # avg power usage of lsq
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avg_regfile_power            0.7699 # avg power usage of arch. regfile
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avg_icache_power             0.6712 # avg power usage of icache
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avg_dcache_power             1.9954 # avg power usage of dcache
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avg_dcache2_power            1.2312 # avg power usage of dcache2
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avg_alu_power                4.8665 # avg power usage of alu
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avg_falu_power               3.6692 # avg power usage of falu
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avg_resultbus_power          0.4994 # avg power usage of resultbus
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avg_clock_power             10.1199 # avg power usage of clock
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fetch_stage_power      76598554212.8761 # total power usage of fetch stage
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dispatch_stage_power   3747581864.9569 # total power usage of dispatch stage
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issue_stage_power      393071326765.2771 # total power usage of issue stage
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avg_fetch_power              1.8146 # average power of fetch unit per cycle
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avg_dispatch_power           0.0888 # average power of dispatch unit per cycle
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avg_issue_power              9.3118 # average power of issue unit per cycle
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total_power            933100432069.2296 # total power per cycle
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avg_total_power_cycle       22.1050 # average total power per cycle
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avg_total_power_cycle_nofp_nod2      17.2047 # average total power per cycle
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avg_total_power_insn        12.8581 # average total power per insn
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avg_total_power_insn_nofp_nod2      10.0076 # average total power per insn
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rename_power_cc1       2555577588.4209 # total power usage of rename unit_cc1
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bpred_power_cc1        10726234733.7591 # total power usage of bpred unit_cc1
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window_power_cc1       17496205670.1672 # total power usage of instruction window_cc1
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lsq_power_cc1          1571667187.9823 # total power usage of lsq_cc1
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regfile_power_cc1      21095786561.1663 # total power usage of arch. regfile_cc1
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icache_power_cc1       20115731464.6774 # total power usage of icache_cc1
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dcache_power_cc1       27203043572.5188 # total power usage of dcache_cc1
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dcache2_power_cc1      3108503858.2429 # total power usage of dcache2_cc1
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alu_power_cc1          36044331258.9081 # total power usage of alu_cc1
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resultbus_power_cc1    14947675709.3777 # total power usage of resultbus_cc1
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clock_power_cc1        148760466508.3615 # total power usage of clock_cc1
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avg_rename_power_cc1         0.0605 # avg power usage of rename unit_cc1
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avg_bpred_power_cc1          0.2541 # avg power usage of bpred unit_cc1
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avg_window_power_cc1         0.4145 # avg power usage of instruction window_cc1
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avg_lsq_power_cc1            0.0372 # avg power usage of lsq_cc1
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avg_regfile_power_cc1        0.4998 # avg power usage of arch. regfile_cc1
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avg_icache_power_cc1         0.4765 # avg power usage of icache_cc1
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avg_dcache_power_cc1         0.6444 # avg power usage of dcache_cc1
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avg_dcache2_power_cc1        0.0736 # avg power usage of dcache2_cc1
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avg_alu_power_cc1            0.8539 # avg power usage of alu_cc1
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avg_resultbus_power_cc1       0.3541 # avg power usage of resultbus_cc1
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avg_clock_power_cc1          3.5241 # avg power usage of clock_cc1
383
fetch_stage_power_cc1  30841966198.4365 # total power usage of fetch stage_cc1
384
dispatch_stage_power_cc1 2555577588.4209 # total power usage of dispatch stage_cc1
385
issue_stage_power_cc1  100371427257.1969 # total power usage of issue stage_cc1
386
avg_fetch_power_cc1          0.7306 # average power of fetch unit per cycle_cc1
387
avg_dispatch_power_cc1       0.0605 # average power of dispatch unit per cycle_cc1
388
avg_issue_power_cc1          2.3778 # average power of issue unit per cycle_cc1
389
total_power_cycle_cc1  303625224113.5820 # total power per cycle_cc1
390
avg_total_power_cycle_cc1       7.1928 # average total power per cycle_cc1
391
avg_total_power_insn_cc1       4.1839 # average total power per insn_cc1
392
rename_power_cc2       1610670335.3298 # total power usage of rename unit_cc2
393
bpred_power_cc2        6878323072.6706 # total power usage of bpred unit_cc2
394
window_power_cc2       12518418350.3719 # total power usage of instruction window_cc2
395
lsq_power_cc2          936829145.4849 # total power usage of lsq_cc2
396
regfile_power_cc2      5202178542.1852 # total power usage of arch. regfile_cc2
397
icache_power_cc2       20115731464.6774 # total power usage of icache_cc2
398
dcache_power_cc2       17661723339.1864 # total power usage of dcache_cc2
399
dcache2_power_cc2      1759661965.5346 # total power usage of dcache2_cc2
400
alu_power_cc2          20056551056.4588 # total power usage of alu_cc2
401
resultbus_power_cc2    8016129108.0042 # total power usage of resultbus_cc2
402
clock_power_cc2        92200037544.4514 # total power usage of clock_cc2
403
avg_rename_power_cc2         0.0382 # avg power usage of rename unit_cc2
404
avg_bpred_power_cc2          0.1629 # avg power usage of bpred unit_cc2
405
avg_window_power_cc2         0.2966 # avg power usage of instruction window_cc2
406
avg_lsq_power_cc2            0.0222 # avg power usage of instruction lsq_cc2
407
avg_regfile_power_cc2        0.1232 # avg power usage of arch. regfile_cc2
408
avg_icache_power_cc2         0.4765 # avg power usage of icache_cc2
409
avg_dcache_power_cc2         0.4184 # avg power usage of dcache_cc2
410
avg_dcache2_power_cc2        0.0417 # avg power usage of dcache2_cc2
411
avg_alu_power_cc2            0.4751 # avg power usage of alu_cc2
412
avg_resultbus_power_cc2       0.1899 # avg power usage of resultbus_cc2
413
avg_clock_power_cc2          2.1842 # avg power usage of clock_cc2
414
fetch_stage_power_cc2  26994054537.3480 # total power usage of fetch stage_cc2
415
dispatch_stage_power_cc2 1610670335.3298 # total power usage of dispatch stage_cc2
416
issue_stage_power_cc2  60949312965.0408 # total power usage of issue stage_cc2
417
avg_fetch_power_cc2          0.6395 # average power of fetch unit per cycle_cc2
418
avg_dispatch_power_cc2       0.0382 # average power of dispatch unit per cycle_cc2
419
avg_issue_power_cc2          1.4439 # average power of issue unit per cycle_cc2
420
total_power_cycle_cc2  186956253924.3553 # total power per cycle_cc2
421
avg_total_power_cycle_cc2       4.4290 # average total power per cycle_cc2
422
avg_total_power_insn_cc2       2.5762 # average total power per insn_cc2
423
rename_power_cc3       1729870680.2731 # total power usage of rename unit_cc3
424
bpred_power_cc3        10634654050.0306 # total power usage of bpred unit_cc3
425
window_power_cc3       12881049037.6976 # total power usage of instruction window_cc3
426
lsq_power_cc3          1627907502.5492 # total power usage of lsq_cc3
427
regfile_power_cc3      6125962463.7474 # total power usage of arch. regfile_cc3
428
icache_power_cc3       20937391089.9910 # total power usage of icache_cc3
429
dcache_power_cc3       23406031296.0216 # total power usage of dcache_cc3
430
dcache2_power_cc3      6645868144.0521 # total power usage of dcache2_cc3
431
alu_power_cc3          36994785967.9134 # total power usage of alu_cc3
432
resultbus_power_cc3    8518378768.7922 # total power usage of resultbus_cc3
433
clock_power_cc3        119711984296.8746 # total power usage of clock_cc3
434
avg_rename_power_cc3         0.0410 # avg power usage of rename unit_cc3
435
avg_bpred_power_cc3          0.2519 # avg power usage of bpred unit_cc3
436
avg_window_power_cc3         0.3052 # avg power usage of instruction window_cc3
437
avg_lsq_power_cc3            0.0386 # avg power usage of instruction lsq_cc3
438
avg_regfile_power_cc3        0.1451 # avg power usage of arch. regfile_cc3
439
avg_icache_power_cc3         0.4960 # avg power usage of icache_cc3
440
avg_dcache_power_cc3         0.5545 # avg power usage of dcache_cc3
441
avg_dcache2_power_cc3        0.1574 # avg power usage of dcache2_cc3
442
avg_alu_power_cc3            0.8764 # avg power usage of alu_cc3
443
avg_resultbus_power_cc3       0.2018 # avg power usage of resultbus_cc3
444
avg_clock_power_cc3          2.8360 # avg power usage of clock_cc3
445
fetch_stage_power_cc3  31572045140.0216 # total power usage of fetch stage_cc3
446
dispatch_stage_power_cc3 1729870680.2731 # total power usage of dispatch stage_cc3
447
issue_stage_power_cc3  90074020717.0261 # total power usage of issue stage_cc3
448
avg_fetch_power_cc3          0.7479 # average power of fetch unit per cycle_cc3
449
avg_dispatch_power_cc3       0.0410 # average power of dispatch unit per cycle_cc3
450
avg_issue_power_cc3          2.1338 # average power of issue unit per cycle_cc3
451
total_power_cycle_cc3  249213883297.9427 # total power per cycle_cc3
452
avg_total_power_cycle_cc3       5.9038 # average total power per cycle_cc3
453
avg_total_power_insn_cc3       3.4342 # average total power per insn_cc3
454
total_rename_access     72569293621 # total number accesses of rename unit
455
total_bpred_access      12031113652 # total number accesses of bpred unit
456
total_window_access    239973583552 # total number accesses of instruction window
457
total_lsq_access        18696519032 # total number accesses of load/store queue
458
total_regfile_access    88808753581 # total number accesses of arch. regfile
459
total_icache_access     75366104710 # total number accesses of icache
460
total_dcache_access     17702251238 # total number accesses of dcache
461
total_dcache2_access     2858534215 # total number accesses of dcache2
462
total_alu_access        67004619708 # total number accesses of alu
463
total_resultbus_access  68994912966 # total number accesses of resultbus
464
avg_rename_access            1.7192 # avg number accesses of rename unit
465
avg_bpred_access             0.2850 # avg number accesses of bpred unit
466
avg_window_access            5.6849 # avg number accesses of instruction window
467
avg_lsq_access               0.4429 # avg number accesses of lsq
468
avg_regfile_access           2.1039 # avg number accesses of arch. regfile
469
avg_icache_access            1.7854 # avg number accesses of icache
470
avg_dcache_access            0.4194 # avg number accesses of dcache
471
avg_dcache2_access           0.0677 # avg number accesses of dcache2
472
avg_alu_access               1.5873 # avg number accesses of alu
473
avg_resultbus_access         1.6345 # avg number accesses of resultbus
474
max_rename_access                 4 # max number accesses of rename unit
475
max_bpred_access                  4 # max number accesses of bpred unit
476
max_window_access                17 # max number accesses of instruction window
477
max_lsq_access                    6 # max number accesses of load/store queue
478
max_regfile_access               12 # max number accesses of arch. regfile
479
max_icache_access                 4 # max number accesses of icache
480
max_dcache_access                 4 # max number accesses of dcache
481
max_dcache2_access                5 # max number accesses of dcache2
482
max_alu_access                    4 # max number accesses of alu
483
max_resultbus_access              9 # max number accesses of resultbus
484
max_cycle_power_cc1         12.8305 # maximum cycle power usage of cc1
485
max_cycle_power_cc2          9.9448 # maximum cycle power usage of cc2
486
max_cycle_power_cc3         10.9548 # maximum cycle power usage of cc3
487
parasitic_power_cc1    25645316687.4515 # parasitic power cc1
488
parasitic_power_cc2    25645316687.4515 # parasitic power cc2
489
parasitic_power_cc3    25645316687.4515 # parasitic power cc3
490
min amperage                 0.0000 # min amperage
491
max amperage                 5.7657 # max amperage
492
slow_cycles                  0.0000 # slow cycles
493
fast_cycles                  0.0000 # fast cycles
494
sim_invalid_addrs                 0 # total non-speculative bogus addresses seen (debug var)
495
ld_text_base             0x00400000 # program text (code) segment base
496
ld_text_size                 237984 # program text (code) size in bytes
497
ld_data_base             0x10000000 # program initialized data segment base
498
ld_data_size                 351008 # program init'ed `.data' and uninit'ed `.bss' size in bytes
499
ld_stack_base            0x7fffc000 # program stack segment base (highest address in stack)
500
ld_stack_size                 16384 # program initial stack size
501
ld_prog_entry            0x00400140 # program entry point (initial PC)
502
ld_environ_base          0x7fff8000 # program environment base address address
503
ld_target_big_endian              0 # target executable endian-ness, non-zero if big endian
504
mem.page_count                49591 # total number of pages allocated
505
mem.page_mem                198364k # total size of memory pages allocated
506
mem.ptab_misses               90778 # total first level page table misses
507
mem.ptab_accesses      189233613744 # total page table accesses
508
mem.ptab_miss_rate           0.0000 # first level page table miss rate
509

    
510

    
511
Cache Parameters:
512
  Size in bytes: 16384
513
  Number of sets: 512
514
  Associativity: 4
515
  Block Size (bytes): 8
516

    
517
Access Time: 9.27925e-09
518
Cycle Time:  1.09081e-08
519

    
520
Best Ndwl (L1): 8
521
Best Ndbl (L1): 1
522
Best Nspd (L1): 1
523
Best Ntwl (L1): 1
524
Best Ntbl (L1): 4
525
Best Ntspd (L1): 1
526

    
527
Time Components:
528
 data side (with Output driver) (ns): 8.44162
529
 tag side (ns): 8.55667
530
 decode_data (ns): 5.29318
531
 wordline_data (ns): 1.03507
532
 bitline_data (ns): 0.810785
533
 sense_amp_data (ns): 0.58
534
 decode_tag (ns): 2.37065
535
 wordline_tag (ns): 1.36749
536
 bitline_tag (ns): 0.158246
537
 sense_amp_tag (ns): 0.26
538
 compare (ns): 2.42991
539
 mux driver (ns): 1.6125
540
 sel inverter (ns): 0.357877
541
 data output driver (ns): 0.722579
542
 total data path (with output driver) (ns): 7.71904
543
 total tag path is set assoc (ns): 8.55667
544
 precharge time (ns): 1.6289
545

    
546
Cache Parameters:
547
  Size in bytes: 16384
548
  Number of sets: 512
549
  Associativity: 1
550
  Block Size (bytes): 32
551

    
552
Access Time: 6.07496e-09
553
Cycle Time:  7.99836e-09
554

    
555
Best Ndwl (L1): 2
556
Best Ndbl (L1): 2
557
Best Nspd (L1): 1
558
Best Ntwl (L1): 1
559
Best Ntbl (L1): 2
560
Best Ntspd (L1): 2
561

    
562
Time Components:
563
 data side (with Output driver) (ns): 6.07496
564
 tag side (ns): 6.05737
565
 decode_data (ns): 2.92313
566
 wordline_data (ns): 1.32956
567
 bitline_data (ns): 0.452976
568
 sense_amp_data (ns): 0.58
569
 decode_tag (ns): 1.84499
570
 wordline_tag (ns): 0.825016
571
 bitline_tag (ns): 0.252886
572
 sense_amp_tag (ns): 0.26
573
 compare (ns): 2.30022
574
 valid signal driver (ns): 0.574251
575
 data output driver (ns): 0.789293
576
 total data path (with output driver) (ns): 5.28567
577
 total tag path is dm (ns): 6.05737
578
 precharge time (ns): 1.92339
579

    
580
Cache Parameters:
581
  Size in bytes: 16384
582
  Number of sets: 128
583
  Associativity: 4
584
  Block Size (bytes): 32
585

    
586
Access Time: 9.14093e-09
587
Cycle Time:  1.11718e-08
588

    
589
Best Ndwl (L1): 4
590
Best Ndbl (L1): 2
591
Best Nspd (L1): 1
592
Best Ntwl (L1): 1
593
Best Ntbl (L1): 2
594
Best Ntspd (L1): 1
595

    
596
Time Components:
597
 data side (with Output driver) (ns): 6.05114
598
 tag side (ns): 7.98848
599
 decode_data (ns): 2.92572
600
 wordline_data (ns): 1.437
601
 bitline_data (ns): -0.0440331
602
 sense_amp_data (ns): 0.58
603
 decode_tag (ns): 1.46851
604
 wordline_tag (ns): 1.27791
605
 bitline_tag (ns): -0.0315811
606
 sense_amp_tag (ns): 0.26
607
 compare (ns): 2.29478
608
 mux driver (ns): 2.37376
609
 sel inverter (ns): 0.345094
610
 data output driver (ns): 1.15245
611
 total data path (with output driver) (ns): 4.89869
612
 total tag path is set assoc (ns): 7.98848
613
 precharge time (ns): 2.03083
614

    
615
Cache Parameters:
616
  Size in bytes: 262144
617
  Number of sets: 1024
618
  Associativity: 4
619
  Block Size (bytes): 64
620

    
621
Access Time: 1.44948e-08
622
Cycle Time:  1.76863e-08
623

    
624
Best Ndwl (L1): 2
625
Best Ndbl (L1): 2
626
Best Nspd (L1): 1
627
Best Ntwl (L1): 1
628
Best Ntbl (L1): 4
629
Best Ntspd (L1): 1
630

    
631
Time Components:
632
 data side (with Output driver) (ns): 11.3269
633
 tag side (ns): 12.2049
634
 decode_data (ns): 4.99158
635
 wordline_data (ns): 2.59771
636
 bitline_data (ns): 0.867749
637
 sense_amp_data (ns): 0.58
638
 decode_tag (ns): 4.52586
639
 wordline_tag (ns): 1.24192
640
 bitline_tag (ns): 0.46158
641
 sense_amp_tag (ns): 0.26
642
 compare (ns): 2.17054
643
 mux driver (ns): 3.21212
644
 sel inverter (ns): 0.332908
645
 data output driver (ns): 2.28987
646
 total data path (with output driver) (ns): 9.03704
647
 total tag path is set assoc (ns): 12.2049
648
 precharge time (ns): 3.19154