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sim-outorder: SimpleScalar/PISA Tool Set version 3.0 of September, 1998.
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Copyright (c) 1994-1998 by Todd M. Austin.  All Rights Reserved.
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Processor Parameters:
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Issue Width: 4
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Window Size: 16
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Number of Virtual Registers: 32
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Number of Physical Registers: 16
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Datapath Width: 64
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Total Power Consumption: 24.105
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Branch Predictor Power Consumption: 1.14342  (5.17%)
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 branch target buffer power (W): 1.04097
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 local predict power (W): 0.0275244
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 global predict power (W): 0.031332
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 chooser power (W): 0.0206036
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 RAS power (W): 0.0229956
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Rename Logic Power Consumption: 0.0887797  (0.402%)
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 Instruction Decode Power (W): 0.0038821
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 RAT decode_power (W): 0.0273861
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 RAT wordline_power (W): 0.00645964
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 RAT bitline_power (W): 0.0486255
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 DCL Comparators (W): 0.0024263
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Instruction Window Power Consumption: 0.517536  (2.34%)
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 tagdrive (W): 0.0186418
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 tagmatch (W): 0.00697769
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 Selection Logic (W): 0.00331194
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 decode_power (W): 0.0131921
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 wordline_power (W): 0.0176803
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 bitline_power (W): 0.457732
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Load/Store Queue Power Consumption: 0.201758  (0.913%)
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 tagdrive (W): 0.0854673
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 tagmatch (W): 0.0207657
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 decode_power (W): 0.00194105
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 wordline_power (W): 0.00302882
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 bitline_power (W): 0.0905553
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Arch. Register File Power Consumption: 0.769909  (3.48%)
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 decode_power (W): 0.0273861
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 wordline_power (W): 0.0176803
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 bitline_power (W): 0.724843
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Result Bus Power Consumption: 0.499392  (2.26%)
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Total Clock Power: 10.1199  (45.8%)
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Int ALU Power: 1.19732  (5.42%)
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FP ALU Power: 3.66922  (16.6%)
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Instruction Cache Power Consumption: 0.614638  (2.78%)
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 decode_power (W): 0.186809
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 wordline_power (W): 0.00542611
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 bitline_power (W): 0.231588
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 senseamp_power (W): 0.07296
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 tagarray_power (W): 0.117856
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Itlb_power (W): 0.0565504 (0.256%)
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Data Cache Power Consumption: 1.80232  (8.15%)
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 decode_power (W): 0.15387
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 wordline_power (W): 0.0368784
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 bitline_power (W): 0.749615
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 senseamp_power (W): 0.58368
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 tagarray_power (W): 0.278274
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Dtlb_power (W): 0.193103 (0.874%)
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Level 2 Cache Power Consumption: 1.23116 (5.57%)
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 decode_power (W): 0.0990259
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 wordline_power (W): 0.00799512
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 bitline_power (W): 0.83087
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 senseamp_power (W): 0.14592
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 tagarray_power (W): 0.147353
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sim: command line: ./sim-outorder gcc00.O2unroll.gcc.100M.ss -funroll-loops -fforce-mem -fcse-follow-jumps -fcse-skip-blocks -fexpensive-optimizations -fstrength-reduce -fpeephole -fschedule-insns -finline-functions -fschedule-insns2 -O regclass.i -o regclass.s 
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sim: simulation started @ Mon Nov 30 16:13:58 2009, options follow:
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sim-outorder: This simulator implements a very detailed out-of-order issue
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superscalar processor with a two-level memory system and speculative
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execution support.  This simulator is a performance simulator, tracking the
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latency of all pipeline operations.
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# -config                     # load configuration from a file
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# -dumpconfig                 # dump configuration to a file
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# -h                    false # print help message    
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# -v                    false # verbose operation     
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# -d                    false # enable debug message  
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# -i                    false # start in Dlite debugger
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-seed                       1 # random number generator seed (0 for timer seed)
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# -q                    false # initialize and terminate immediately
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# -chkpt               <null> # restore EIO trace execution from <fname>
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# -redir:sim           <null> # redirect simulator output to file (non-interactive only)
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# -redir:prog          <null> # redirect simulated program output to file
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-nice                       0 # simulator scheduling priority
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-max:inst                   0 # maximum number of inst's to execute
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-fastfwd                    0 # number of insts skipped before timing starts
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# -ptrace              <null> # generate pipetrace, i.e., <fname|stdout|stderr> <range>
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-fetch:ifqsize              4 # instruction fetch queue size (in insts)
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-fetch:mplat                3 # extra branch mis-prediction latency
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-fetch:speed                1 # speed of front-end of machine relative to execution core
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-bpred                  bimod # branch predictor type {nottaken|taken|perfect|bimod|2lev|comb}
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-bpred:bimod     2048 # bimodal predictor config (<table size>)
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-bpred:2lev      1 1024 8 0 # 2-level predictor config (<l1size> <l2size> <hist_size> <xor>)
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-bpred:comb      1024 # combining predictor config (<meta_table_size>)
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-bpred:ras                  8 # return address stack size (0 for no return stack)
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-bpred:btb       512 4 # BTB config (<num_sets> <associativity>)
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# -bpred:spec_update       <null> # speculative predictors update in {ID|WB} (default non-spec)
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-decode:width               4 # instruction decode B/W (insts/cycle)
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-issue:width                4 # instruction issue B/W (insts/cycle)
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-issue:inorder          false # run pipeline with in-order issue
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-issue:wrongpath         true # issue instructions down wrong execution paths
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-commit:width               4 # instruction commit B/W (insts/cycle)
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-ruu:size                  16 # register update unit (RUU) size
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-lsq:size                   8 # load/store queue (LSQ) size
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-cache:dl1       dl1:128:32:4:l # l1 data cache config, i.e., {<config>|none}
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-cache:dl1lat               1 # l1 data cache hit latency (in cycles)
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-cache:dl2       ul2:1024:64:4:l # l2 data cache config, i.e., {<config>|none}
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-cache:dl2lat               6 # l2 data cache hit latency (in cycles)
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-cache:il1       il1:512:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2|none}
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-cache:il1lat               1 # l1 instruction cache hit latency (in cycles)
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-cache:il2                dl2 # l2 instruction cache config, i.e., {<config>|dl2|none}
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-cache:il2lat               6 # l2 instruction cache hit latency (in cycles)
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-cache:flush            false # flush caches on system calls
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-cache:icompress        false # convert 64-bit inst addresses to 32-bit inst equivalents
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-mem:lat         18 2 # memory access latency (<first_chunk> <inter_chunk>)
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-mem:width                  8 # memory access bus width (in bytes)
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-tlb:itlb        itlb:16:4096:4:l # instruction TLB config, i.e., {<config>|none}
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-tlb:dtlb        dtlb:32:4096:4:l # data TLB config, i.e., {<config>|none}
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-tlb:lat                   30 # inst/data TLB miss latency (in cycles)
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-res:ialu                   4 # total number of integer ALU's available
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-res:imult                  1 # total number of integer multiplier/dividers available
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-res:memport                2 # total number of memory system ports available (to CPU)
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-res:fpalu                  4 # total number of floating point ALU's available
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-res:fpmult                 1 # total number of floating point multiplier/dividers available
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# -pcstat              <null> # profile stat(s) against text addr's (mult uses ok)
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-bugcompat              false # operate in backward-compatible bugs mode (for testing only)
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  Pipetrace range arguments are formatted as follows:
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    {{@|#}<start>}:{{@|#|+}<end>}
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  Both ends of the range are optional, if neither are specified, the entire
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  execution is traced.  Ranges that start with a `@' designate an address
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  range to be traced, those that start with an `#' designate a cycle count
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  range.  All other range values represent an instruction count range.  The
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  second argument, if specified with a `+', indicates a value relative
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  to the first argument, e.g., 1000:+100 == 1000:1100.  Program symbols may
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  be used in all contexts.
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    Examples:   -ptrace FOO.trc #0:#1000
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                -ptrace BAR.trc @2000:
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                -ptrace BLAH.trc :1500
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                -ptrace UXXE.trc :
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                -ptrace FOOBAR.trc @main:+278
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  Branch predictor configuration examples for 2-level predictor:
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    Configurations:   N, M, W, X
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      N   # entries in first level (# of shift register(s))
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      W   width of shift register(s)
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      M   # entries in 2nd level (# of counters, or other FSM)
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      X   (yes-1/no-0) xor history and address for 2nd level index
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    Sample predictors:
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      GAg     : 1, W, 2^W, 0
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      GAp     : 1, W, M (M > 2^W), 0
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      PAg     : N, W, 2^W, 0
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      PAp     : N, W, M (M == 2^(N+W)), 0
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      gshare  : 1, W, 2^W, 1
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  Predictor `comb' combines a bimodal and a 2-level predictor.
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  The cache config parameter <config> has the following format:
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    <name>:<nsets>:<bsize>:<assoc>:<repl>
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    <name>   - name of the cache being defined
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    <nsets>  - number of sets in the cache
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    <bsize>  - block size of the cache
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    <assoc>  - associativity of the cache
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    <repl>   - block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random
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    Examples:   -cache:dl1 dl1:4096:32:1:l
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                -dtlb dtlb:128:4096:32:r
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  Cache levels can be unified by pointing a level of the instruction cache
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  hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache
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  configuration arguments.  Most sensible combinations are supported, e.g.,
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    A unified l2 cache (il2 is pointed at dl2):
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      -cache:il1 il1:128:64:1:l -cache:il2 dl2
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      -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
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    Or, a fully unified cache hierarchy (il1 pointed at dl1):
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      -cache:il1 dl1
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      -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
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sim: ** starting performance simulation **
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warning: syscall: sigvec ignored
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warning: syscall: sigvec ignored
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 init_reg_sets init_reg_sets_1 fix_register reg_preferred_class reg_preferred_or_nothing regclass_init regclass reg_class_record record_address_regs reg_scan reg_scan_mark_refs
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time in parse: 15.464966
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time in integration: 1.220076
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time in jump: 7.580472
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time in cse: 23.113446
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time in loop: 9.452590
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time in cse2: 41.490594
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time in flow: 6.820425
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time in combine: 33.282081
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time in sched: 9.000563
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time in local-alloc: 11.676730
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time in global-alloc: 12.232766
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time in sched2: 6.980437
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time in dbranch: 17.545095
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time in shorten-branch: 0.388026
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time in stack-reg: 0.000000
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time in final: 7.112443
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time in varconst: 0.216014
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time in symout: 0.000000
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time in dump: 0.000000
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sim: ** simulation statistics **
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sim_num_insn              172200679 # total number of instructions committed
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sim_num_refs               68343556 # total number of loads and stores committed
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sim_num_loads              44498289 # total number of loads committed
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sim_num_stores         23845267.0000 # total number of stores committed
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sim_num_branches           35305345 # total number of branches committed
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sim_elapsed_time                208 # total simulation time in seconds
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sim_inst_rate           827887.8798 # simulation speed (in insts/sec)
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sim_total_insn            201110265 # total number of instructions executed
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sim_total_refs             79004211 # total number of loads and stores executed
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sim_total_loads            53353323 # total number of loads executed
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sim_total_stores       25650888.0000 # total number of stores executed
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sim_total_branches         41270170 # total number of branches executed
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sim_cycle                 185516905 # total simulation time in cycles
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sim_IPC                      0.9282 # instructions per cycle
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sim_CPI                      1.0773 # cycles per instruction
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sim_exec_BW                  1.0841 # total instructions (mis-spec + committed) per cycle
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sim_IPB                      4.8775 # instruction per branch
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IFQ_count                 289260070 # cumulative IFQ occupancy
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IFQ_fcount                 60074054 # cumulative IFQ full count
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ifq_occupancy                1.5592 # avg IFQ occupancy (insn's)
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ifq_rate                     1.0841 # avg IFQ dispatch rate (insn/cycle)
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ifq_latency                  1.4383 # avg IFQ occupant latency (cycle's)
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ifq_full                     0.3238 # fraction of time (cycle's) IFQ was full
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RUU_count                1039737033 # cumulative RUU occupancy
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RUU_fcount                 20165698 # cumulative RUU full count
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ruu_occupancy                5.6045 # avg RUU occupancy (insn's)
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ruu_rate                     1.0841 # avg RUU dispatch rate (insn/cycle)
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ruu_latency                  5.1700 # avg RUU occupant latency (cycle's)
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ruu_full                     0.1087 # fraction of time (cycle's) RUU was full
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LSQ_count                 416172678 # cumulative LSQ occupancy
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LSQ_fcount                 16765980 # cumulative LSQ full count
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lsq_occupancy                2.2433 # avg LSQ occupancy (insn's)
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lsq_rate                     1.0841 # avg LSQ dispatch rate (insn/cycle)
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lsq_latency                  2.0694 # avg LSQ occupant latency (cycle's)
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lsq_full                     0.0904 # fraction of time (cycle's) LSQ was full
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bpred_bimod.lookups        43325430 # total number of bpred lookups
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bpred_bimod.updates        35305345 # total number of updates
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bpred_bimod.addr_hits      30829029 # total number of address-predicted hits
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bpred_bimod.dir_hits       31597185 # total number of direction-predicted hits (includes addr-hits)
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bpred_bimod.misses          3708160 # total number of misses
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bpred_bimod.jr_hits         2853180 # total number of address-predicted hits for JR's
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bpred_bimod.jr_seen         3578275 # total number of JR's seen
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bpred_bimod.jr_non_ras_hits.PP       317354 # total number of address-predicted hits for non-RAS JR's
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bpred_bimod.jr_non_ras_seen.PP       965369 # total number of non-RAS JR's seen
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bpred_bimod.bpred_addr_rate    0.8732 # branch address-prediction rate (i.e., addr-hits/updates)
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bpred_bimod.bpred_dir_rate    0.8950 # branch direction-prediction rate (i.e., all-hits/updates)
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bpred_bimod.bpred_jr_rate    0.7974 # JR address-prediction rate (i.e., JR addr-hits/JRs seen)
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bpred_bimod.bpred_jr_non_ras_rate.PP    0.3287 # non-RAS JR addr-pred rate (ie, non-RAS JR hits/JRs seen)
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bpred_bimod.retstack_pushes      3240181 # total number of address pushed onto ret-addr stack
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bpred_bimod.retstack_pops      3023017 # total number of address popped off of ret-addr stack
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bpred_bimod.used_ras.PP      2612906 # total number of RAS predictions used
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bpred_bimod.ras_hits.PP      2535826 # total number of RAS hits
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bpred_bimod.ras_rate.PP    0.9705 # RAS prediction rate (i.e., RAS hits/used RAS)
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il1.accesses              224882137 # total number of accesses
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il1.hits                  210152805 # total number of hits
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il1.misses                 14729332 # total number of misses
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il1.replacements           14728820 # total number of replacements
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il1.writebacks                    0 # total number of writebacks
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il1.invalidations                 0 # total number of invalidations
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il1.miss_rate                0.0655 # miss rate (i.e., misses/ref)
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il1.repl_rate                0.0655 # replacement rate (i.e., repls/ref)
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il1.wb_rate                  0.0000 # writeback rate (i.e., wrbks/ref)
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il1.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)
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dl1.accesses               71738947 # total number of accesses
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dl1.hits                   70588778 # total number of hits
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dl1.misses                  1150169 # total number of misses
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dl1.replacements            1149657 # total number of replacements
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dl1.writebacks               351145 # total number of writebacks
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dl1.invalidations                 0 # total number of invalidations
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dl1.miss_rate                0.0160 # miss rate (i.e., misses/ref)
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dl1.repl_rate                0.0160 # replacement rate (i.e., repls/ref)
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dl1.wb_rate                  0.0049 # writeback rate (i.e., wrbks/ref)
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dl1.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)
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ul2.accesses               16230646 # total number of accesses
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ul2.hits                   15915666 # total number of hits
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ul2.misses                   314980 # total number of misses
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ul2.replacements             310884 # total number of replacements
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ul2.writebacks                57635 # total number of writebacks
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ul2.invalidations                 0 # total number of invalidations
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ul2.miss_rate                0.0194 # miss rate (i.e., misses/ref)
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ul2.repl_rate                0.0192 # replacement rate (i.e., repls/ref)
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ul2.wb_rate                  0.0036 # writeback rate (i.e., wrbks/ref)
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ul2.inv_rate                 0.0000 # invalidation rate (i.e., invs/ref)
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itlb.accesses             224882137 # total number of accesses
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itlb.hits                 224791405 # total number of hits
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itlb.misses                   90732 # total number of misses
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itlb.replacements             90668 # total number of replacements
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itlb.writebacks                   0 # total number of writebacks
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itlb.invalidations                0 # total number of invalidations
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itlb.miss_rate               0.0004 # miss rate (i.e., misses/ref)
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itlb.repl_rate               0.0004 # replacement rate (i.e., repls/ref)
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itlb.wb_rate                 0.0000 # writeback rate (i.e., wrbks/ref)
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itlb.inv_rate                0.0000 # invalidation rate (i.e., invs/ref)
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dtlb.accesses              72156358 # total number of accesses
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dtlb.hits                  72154170 # total number of hits
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dtlb.misses                    2188 # total number of misses
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dtlb.replacements              2060 # total number of replacements
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dtlb.writebacks                   0 # total number of writebacks
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dtlb.invalidations                0 # total number of invalidations
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dtlb.miss_rate               0.0000 # miss rate (i.e., misses/ref)
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dtlb.repl_rate               0.0000 # replacement rate (i.e., repls/ref)
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dtlb.wb_rate                 0.0000 # writeback rate (i.e., wrbks/ref)
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dtlb.inv_rate                0.0000 # invalidation rate (i.e., invs/ref)
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rename_power           16470141.9026 # total power usage of rename unit
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bpred_power            212124211.5734 # total power usage of bpred unit
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window_power           96011717.5794 # total power usage of instruction window
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lsq_power              37429548.8516 # total power usage of load/store queue
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regfile_power          142831198.0535 # total power usage of arch. regfile
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icache_power           124516839.4225 # total power usage of icache
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dcache_power           370184282.6854 # total power usage of dcache
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dcache2_power          228401693.6754 # total power usage of dcache2
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alu_power              902825281.9901 # total power usage of alu
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falu_power             680701603.0320 # total power usage of falu
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resultbus_power        92645733.3963 # total power usage of resultbus
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clock_power            1877416637.3875 # total power usage of clock
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avg_rename_power             0.0888 # avg power usage of rename unit
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avg_bpred_power              1.1434 # avg power usage of bpred unit
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avg_window_power             0.5175 # avg power usage of instruction window
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avg_lsq_power                0.2018 # avg power usage of lsq
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avg_regfile_power            0.7699 # avg power usage of arch. regfile
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avg_icache_power             0.6712 # avg power usage of icache
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avg_dcache_power             1.9954 # avg power usage of dcache
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avg_dcache2_power            1.2312 # avg power usage of dcache2
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avg_alu_power                4.8665 # avg power usage of alu
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avg_falu_power               3.6692 # avg power usage of falu
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avg_resultbus_power          0.4994 # avg power usage of resultbus
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avg_clock_power             10.1199 # avg power usage of clock
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fetch_stage_power      336641050.9959 # total power usage of fetch stage
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dispatch_stage_power   16470141.9026 # total power usage of dispatch stage
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issue_stage_power      1727498258.1783 # total power usage of issue stage
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avg_fetch_power              1.8146 # average power of fetch unit per cycle
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avg_dispatch_power           0.0888 # average power of dispatch unit per cycle
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avg_issue_power              9.3118 # average power of issue unit per cycle
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total_power            4100857286.5178 # total power per cycle
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avg_total_power_cycle       22.1050 # average total power per cycle
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avg_total_power_cycle_nofp_nod2      17.2047 # average total power per cycle
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avg_total_power_insn        20.3911 # average total power per insn
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avg_total_power_insn_nofp_nod2      15.8707 # average total power per insn
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rename_power_cc1       6255367.5696 # total power usage of rename unit_cc1
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bpred_power_cc1        33922564.4640 # total power usage of bpred unit_cc1
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window_power_cc1       61689071.5993 # total power usage of instruction window_cc1
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lsq_power_cc1          4932853.0010 # total power usage of lsq_cc1
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regfile_power_cc1      69046167.5108 # total power usage of arch. regfile_cc1
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icache_power_cc1       56747432.6709 # total power usage of icache_cc1
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dcache_power_cc1       98161450.7489 # total power usage of dcache_cc1
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dcache2_power_cc1      19493839.1810 # total power usage of dcache2_cc1
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alu_power_cc1          98850959.1105 # total power usage of alu_cc1
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resultbus_power_cc1    42967212.4817 # total power usage of resultbus_cc1
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clock_power_cc1        438683281.2330 # total power usage of clock_cc1
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avg_rename_power_cc1         0.0337 # avg power usage of rename unit_cc1
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avg_bpred_power_cc1          0.1829 # avg power usage of bpred unit_cc1
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avg_window_power_cc1         0.3325 # avg power usage of instruction window_cc1
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avg_lsq_power_cc1            0.0266 # avg power usage of lsq_cc1
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avg_regfile_power_cc1        0.3722 # avg power usage of arch. regfile_cc1
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avg_icache_power_cc1         0.3059 # avg power usage of icache_cc1
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avg_dcache_power_cc1         0.5291 # avg power usage of dcache_cc1
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avg_dcache2_power_cc1        0.1051 # avg power usage of dcache2_cc1
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avg_alu_power_cc1            0.5328 # avg power usage of alu_cc1
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avg_resultbus_power_cc1       0.2316 # avg power usage of resultbus_cc1
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avg_clock_power_cc1          2.3647 # avg power usage of clock_cc1
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fetch_stage_power_cc1  90669997.1349 # total power usage of fetch stage_cc1
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dispatch_stage_power_cc1 6255367.5696 # total power usage of dispatch stage_cc1
375
issue_stage_power_cc1  326095386.1224 # total power usage of issue stage_cc1
376
avg_fetch_power_cc1          0.4887 # average power of fetch unit per cycle_cc1
377
avg_dispatch_power_cc1       0.0337 # average power of dispatch unit per cycle_cc1
378
avg_issue_power_cc1          1.7578 # average power of issue unit per cycle_cc1
379
total_power_cycle_cc1  930750199.5707 # total power per cycle_cc1
380
avg_total_power_cycle_cc1       5.0171 # average total power per cycle_cc1
381
avg_total_power_insn_cc1       4.6281 # average total power per insn_cc1
382
rename_power_cc2       4449755.9489 # total power usage of rename unit_cc2
383
bpred_power_cc2        20184463.7519 # total power usage of bpred unit_cc2
384
window_power_cc2       37365036.6849 # total power usage of instruction window_cc2
385
lsq_power_cc2          3406654.5071 # total power usage of lsq_cc2
386
regfile_power_cc2      14719209.8716 # total power usage of arch. regfile_cc2
387
icache_power_cc2       56747432.6709 # total power usage of icache_cc2
388
dcache_power_cc2       71574692.0482 # total power usage of dcache_cc2
389
dcache2_power_cc2      9991291.7505 # total power usage of dcache2_cc2
390
alu_power_cc2          54166582.3126 # total power usage of alu_cc2
391
resultbus_power_cc2    23934468.8636 # total power usage of resultbus_cc2
392
clock_power_cc2        264877804.5740 # total power usage of clock_cc2
393
avg_rename_power_cc2         0.0240 # avg power usage of rename unit_cc2
394
avg_bpred_power_cc2          0.1088 # avg power usage of bpred unit_cc2
395
avg_window_power_cc2         0.2014 # avg power usage of instruction window_cc2
396
avg_lsq_power_cc2            0.0184 # avg power usage of instruction lsq_cc2
397
avg_regfile_power_cc2        0.0793 # avg power usage of arch. regfile_cc2
398
avg_icache_power_cc2         0.3059 # avg power usage of icache_cc2
399
avg_dcache_power_cc2         0.3858 # avg power usage of dcache_cc2
400
avg_dcache2_power_cc2        0.0539 # avg power usage of dcache2_cc2
401
avg_alu_power_cc2            0.2920 # avg power usage of alu_cc2
402
avg_resultbus_power_cc2       0.1290 # avg power usage of resultbus_cc2
403
avg_clock_power_cc2          1.4278 # avg power usage of clock_cc2
404
fetch_stage_power_cc2  76931896.4228 # total power usage of fetch stage_cc2
405
dispatch_stage_power_cc2 4449755.9489 # total power usage of dispatch stage_cc2
406
issue_stage_power_cc2  200438726.1668 # total power usage of issue stage_cc2
407
avg_fetch_power_cc2          0.4147 # average power of fetch unit per cycle_cc2
408
avg_dispatch_power_cc2       0.0240 # average power of dispatch unit per cycle_cc2
409
avg_issue_power_cc2          1.0804 # average power of issue unit per cycle_cc2
410
total_power_cycle_cc2  561417392.9841 # total power per cycle_cc2
411
avg_total_power_cycle_cc2       3.0262 # average total power per cycle_cc2
412
avg_total_power_insn_cc2       2.7916 # average total power per insn_cc2
413
rename_power_cc3       5471233.3871 # total power usage of rename unit_cc3
414
bpred_power_cc3        38035307.2647 # total power usage of bpred unit_cc3
415
window_power_cc3       40548570.1362 # total power usage of instruction window_cc3
416
lsq_power_cc3          6632040.4057 # total power usage of lsq_cc3
417
regfile_power_cc3      21484896.1788 # total power usage of arch. regfile_cc3
418
icache_power_cc3       63524373.2445 # total power usage of icache_cc3
419
dcache_power_cc3       99005370.7658 # total power usage of dcache_cc3
420
dcache2_power_cc3      30883485.3575 # total power usage of dcache2_cc3
421
alu_power_cc3          134564015.2650 # total power usage of alu_cc3
422
resultbus_power_cc3    28782864.8730 # total power usage of resultbus_cc3
423
clock_power_cc3        408044203.0867 # total power usage of clock_cc3
424
avg_rename_power_cc3         0.0295 # avg power usage of rename unit_cc3
425
avg_bpred_power_cc3          0.2050 # avg power usage of bpred unit_cc3
426
avg_window_power_cc3         0.2186 # avg power usage of instruction window_cc3
427
avg_lsq_power_cc3            0.0357 # avg power usage of instruction lsq_cc3
428
avg_regfile_power_cc3        0.1158 # avg power usage of arch. regfile_cc3
429
avg_icache_power_cc3         0.3424 # avg power usage of icache_cc3
430
avg_dcache_power_cc3         0.5337 # avg power usage of dcache_cc3
431
avg_dcache2_power_cc3        0.1665 # avg power usage of dcache2_cc3
432
avg_alu_power_cc3            0.7253 # avg power usage of alu_cc3
433
avg_resultbus_power_cc3       0.1551 # avg power usage of resultbus_cc3
434
avg_clock_power_cc3          2.1995 # avg power usage of clock_cc3
435
fetch_stage_power_cc3  101559680.5093 # total power usage of fetch stage_cc3
436
dispatch_stage_power_cc3 5471233.3871 # total power usage of dispatch stage_cc3
437
issue_stage_power_cc3  340416346.8032 # total power usage of issue stage_cc3
438
avg_fetch_power_cc3          0.5474 # average power of fetch unit per cycle_cc3
439
avg_dispatch_power_cc3       0.0295 # average power of dispatch unit per cycle_cc3
440
avg_issue_power_cc3          1.8350 # average power of issue unit per cycle_cc3
441
total_power_cycle_cc3  876976359.9651 # total power per cycle_cc3
442
avg_total_power_cycle_cc3       4.7272 # average total power per cycle_cc3
443
avg_total_power_insn_cc3       4.3607 # average total power per insn_cc3
444
total_rename_access       200485207 # total number accesses of rename unit
445
total_bpred_access         35305345 # total number accesses of bpred unit
446
total_window_access       729803289 # total number accesses of instruction window
447
total_lsq_access           73117408 # total number accesses of load/store queue
448
total_regfile_access      254805012 # total number accesses of arch. regfile
449
total_icache_access       225607983 # total number accesses of icache
450
total_dcache_access        71738947 # total number accesses of dcache
451
total_dcache2_access       16230646 # total number accesses of dcache2
452
total_alu_access          180946144 # total number accesses of alu
453
total_resultbus_access    196891185 # total number accesses of resultbus
454
avg_rename_access            1.0807 # avg number accesses of rename unit
455
avg_bpred_access             0.1903 # avg number accesses of bpred unit
456
avg_window_access            3.9339 # avg number accesses of instruction window
457
avg_lsq_access               0.3941 # avg number accesses of lsq
458
avg_regfile_access           1.3735 # avg number accesses of arch. regfile
459
avg_icache_access            1.2161 # avg number accesses of icache
460
avg_dcache_access            0.3867 # avg number accesses of dcache
461
avg_dcache2_access           0.0875 # avg number accesses of dcache2
462
avg_alu_access               0.9754 # avg number accesses of alu
463
avg_resultbus_access         1.0613 # avg number accesses of resultbus
464
max_rename_access                 4 # max number accesses of rename unit
465
max_bpred_access                  4 # max number accesses of bpred unit
466
max_window_access                17 # max number accesses of instruction window
467
max_lsq_access                    6 # max number accesses of load/store queue
468
max_regfile_access               12 # max number accesses of arch. regfile
469
max_icache_access                 4 # max number accesses of icache
470
max_dcache_access                 4 # max number accesses of dcache
471
max_dcache2_access                7 # max number accesses of dcache2
472
max_alu_access                    4 # max number accesses of alu
473
max_resultbus_access              8 # max number accesses of resultbus
474
max_cycle_power_cc1         12.1199 # maximum cycle power usage of cc1
475
max_cycle_power_cc2          9.6089 # maximum cycle power usage of cc2
476
max_cycle_power_cc3         10.7516 # maximum cycle power usage of cc3
477
parasitic_power_cc1    100996684.9694 # parasitic power cc1
478
parasitic_power_cc2    100996684.9694 # parasitic power cc2
479
parasitic_power_cc3    100996684.9694 # parasitic power cc3
480
min amperage                 0.0000 # min amperage
481
max amperage                 5.6587 # max amperage
482
slow_cycles                  0.0000 # slow cycles
483
fast_cycles                  0.0000 # fast cycles
484
sim_invalid_addrs                 0 # total non-speculative bogus addresses seen (debug var)
485
ld_text_base             0x00400000 # program text (code) segment base
486
ld_text_size                2485696 # program text (code) size in bytes
487
ld_data_base             0x10000000 # program initialized data segment base
488
ld_data_size                 287696 # program init'ed `.data' and uninit'ed `.bss' size in bytes
489
ld_stack_base            0x7fffc000 # program stack segment base (highest address in stack)
490
ld_stack_size                 16384 # program initial stack size
491
ld_prog_entry            0x00400140 # program entry point (initial PC)
492
ld_environ_base          0x7fff8000 # program environment base address address
493
ld_target_big_endian              0 # target executable endian-ness, non-zero if big endian
494
mem.page_count                  873 # total number of pages allocated
495
mem.page_mem                  3492k # total size of memory pages allocated
496
mem.ptab_misses                9978 # total first level page table misses
497
mem.ptab_accesses         609996197 # total page table accesses
498
mem.ptab_miss_rate           0.0000 # first level page table miss rate
499

    
500

    
501
Cache Parameters:
502
  Size in bytes: 16384
503
  Number of sets: 512
504
  Associativity: 4
505
  Block Size (bytes): 8
506

    
507
Access Time: 9.27925e-09
508
Cycle Time:  1.09081e-08
509

    
510
Best Ndwl (L1): 8
511
Best Ndbl (L1): 1
512
Best Nspd (L1): 1
513
Best Ntwl (L1): 1
514
Best Ntbl (L1): 4
515
Best Ntspd (L1): 1
516

    
517
Time Components:
518
 data side (with Output driver) (ns): 8.44162
519
 tag side (ns): 8.55667
520
 decode_data (ns): 5.29318
521
 wordline_data (ns): 1.03507
522
 bitline_data (ns): 0.810785
523
 sense_amp_data (ns): 0.58
524
 decode_tag (ns): 2.37065
525
 wordline_tag (ns): 1.36749
526
 bitline_tag (ns): 0.158246
527
 sense_amp_tag (ns): 0.26
528
 compare (ns): 2.42991
529
 mux driver (ns): 1.6125
530
 sel inverter (ns): 0.357877
531
 data output driver (ns): 0.722579
532
 total data path (with output driver) (ns): 7.71904
533
 total tag path is set assoc (ns): 8.55667
534
 precharge time (ns): 1.6289
535

    
536
Cache Parameters:
537
  Size in bytes: 16384
538
  Number of sets: 512
539
  Associativity: 1
540
  Block Size (bytes): 32
541

    
542
Access Time: 6.07496e-09
543
Cycle Time:  7.99836e-09
544

    
545
Best Ndwl (L1): 2
546
Best Ndbl (L1): 2
547
Best Nspd (L1): 1
548
Best Ntwl (L1): 1
549
Best Ntbl (L1): 2
550
Best Ntspd (L1): 2
551

    
552
Time Components:
553
 data side (with Output driver) (ns): 6.07496
554
 tag side (ns): 6.05737
555
 decode_data (ns): 2.92313
556
 wordline_data (ns): 1.32956
557
 bitline_data (ns): 0.452976
558
 sense_amp_data (ns): 0.58
559
 decode_tag (ns): 1.84499
560
 wordline_tag (ns): 0.825016
561
 bitline_tag (ns): 0.252886
562
 sense_amp_tag (ns): 0.26
563
 compare (ns): 2.30022
564
 valid signal driver (ns): 0.574251
565
 data output driver (ns): 0.789293
566
 total data path (with output driver) (ns): 5.28567
567
 total tag path is dm (ns): 6.05737
568
 precharge time (ns): 1.92339
569

    
570
Cache Parameters:
571
  Size in bytes: 16384
572
  Number of sets: 128
573
  Associativity: 4
574
  Block Size (bytes): 32
575

    
576
Access Time: 9.14093e-09
577
Cycle Time:  1.11718e-08
578

    
579
Best Ndwl (L1): 4
580
Best Ndbl (L1): 2
581
Best Nspd (L1): 1
582
Best Ntwl (L1): 1
583
Best Ntbl (L1): 2
584
Best Ntspd (L1): 1
585

    
586
Time Components:
587
 data side (with Output driver) (ns): 6.05114
588
 tag side (ns): 7.98848
589
 decode_data (ns): 2.92572
590
 wordline_data (ns): 1.437
591
 bitline_data (ns): -0.0440331
592
 sense_amp_data (ns): 0.58
593
 decode_tag (ns): 1.46851
594
 wordline_tag (ns): 1.27791
595
 bitline_tag (ns): -0.0315811
596
 sense_amp_tag (ns): 0.26
597
 compare (ns): 2.29478
598
 mux driver (ns): 2.37376
599
 sel inverter (ns): 0.345094
600
 data output driver (ns): 1.15245
601
 total data path (with output driver) (ns): 4.89869
602
 total tag path is set assoc (ns): 7.98848
603
 precharge time (ns): 2.03083
604

    
605
Cache Parameters:
606
  Size in bytes: 262144
607
  Number of sets: 1024
608
  Associativity: 4
609
  Block Size (bytes): 64
610

    
611
Access Time: 1.44948e-08
612
Cycle Time:  1.76863e-08
613

    
614
Best Ndwl (L1): 2
615
Best Ndbl (L1): 2
616
Best Nspd (L1): 1
617
Best Ntwl (L1): 1
618
Best Ntbl (L1): 4
619
Best Ntspd (L1): 1
620

    
621
Time Components:
622
 data side (with Output driver) (ns): 11.3269
623
 tag side (ns): 12.2049
624
 decode_data (ns): 4.99158
625
 wordline_data (ns): 2.59771
626
 bitline_data (ns): 0.867749
627
 sense_amp_data (ns): 0.58
628
 decode_tag (ns): 4.52586
629
 wordline_tag (ns): 1.24192
630
 bitline_tag (ns): 0.46158
631
 sense_amp_tag (ns): 0.26
632
 compare (ns): 2.17054
633
 mux driver (ns): 3.21212
634
 sel inverter (ns): 0.332908
635
 data output driver (ns): 2.28987
636
 total data path (with output driver) (ns): 9.03704
637
 total tag path is set assoc (ns): 12.2049
638
 precharge time (ns): 3.19154