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extern int target_flags;
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enum reg_class { NO_REGS, LO_FPA_REGS, FPA_REGS, FP_REGS,
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  FP_OR_FPA_REGS, DATA_REGS, DATA_OR_FPA_REGS, DATA_OR_FP_REGS,
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  DATA_OR_FP_OR_FPA_REGS, ADDR_REGS, GENERAL_REGS,
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  GENERAL_OR_FPA_REGS, GENERAL_OR_FP_REGS, ALL_REGS,
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  LIM_REG_CLASSES };
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extern enum reg_class regno_reg_class[];
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enum rtx_code  {
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  UNKNOWN , 
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  NIL , 
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  EXPR_LIST , 
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  INSN_LIST , 
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  MATCH_OPERAND , 
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  MATCH_DUP , 
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  MATCH_OPERATOR , 
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  DEFINE_INSN , 
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  DEFINE_PEEPHOLE , 
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  DEFINE_COMBINE , 
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  DEFINE_EXPAND , 
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  SEQUENCE , 
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  ADDRESS , 
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  INSN , 
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  JUMP_INSN , 
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  CALL_INSN , 
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  BARRIER , 
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  CODE_LABEL , 
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  NOTE , 
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  INLINE_HEADER , 
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  PARALLEL , 
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  ASM_INPUT , 
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  ASM_OPERANDS , 
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  ADDR_VEC , 
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  ADDR_DIFF_VEC , 
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  SET , 
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  USE , 
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  CLOBBER , 
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  CALL , 
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  RETURN , 
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  CONST_INT , 
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  CONST_DOUBLE , 
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  CONST , 
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  PC , 
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  REG , 
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  SUBREG , 
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  STRICT_LOW_PART , 
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  MEM , 
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  LABEL_REF , 
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  SYMBOL_REF , 
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  CC0 , 
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  QUEUED , 
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  IF_THEN_ELSE , 
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  COMPARE , 
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  PLUS , 
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  MINUS , 
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  NEG , 
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  MULT , 
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  DIV , 
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  MOD , 
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  UMULT , 
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  UDIV , 
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  UMOD , 
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  AND , 
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  IOR , 
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  XOR , 
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  NOT , 
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  LSHIFT , 
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  ASHIFT , 
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  ROTATE , 
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  ASHIFTRT , 
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  LSHIFTRT , 
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  ROTATERT , 
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  PRE_DEC , 
134
  PRE_INC , 
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  POST_DEC , 
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  POST_INC , 
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  NE , 
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  EQ , 
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  GE , 
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  GT , 
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  LE , 
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  LT , 
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  GEU , 
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  GTU , 
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  LEU , 
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  LTU , 
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  SIGN_EXTEND , 
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  ZERO_EXTEND , 
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  TRUNCATE , 
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  FLOAT_EXTEND , 
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  FLOAT_TRUNCATE , 
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  FLOAT , 
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  FIX , 
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  UNSIGNED_FLOAT , 
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  UNSIGNED_FIX , 
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  ABS , 
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  SQRT , 
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  FFS , 
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  SIGN_EXTRACT , 
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  ZERO_EXTRACT , 
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  LAST_AND_UNUSED_RTX_CODE};	 
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extern int rtx_length[];
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extern char *rtx_name[];
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extern char *rtx_format[];
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enum machine_mode {
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 VOIDmode, 
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 QImode, 		 
189
 HImode, 
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 PSImode, 
192
 SImode, 
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 PDImode, 
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 DImode, 
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 TImode, 
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 QFmode, 
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 HFmode, 		 
198
 SFmode, 
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 DFmode, 
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 XFmode, 	 
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 TFmode, 
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 CQImode, 
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 CHImode, 	 
204
 CSImode, 
205
 CDImode, 
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 CTImode, 
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 CQFmode, 
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 CHFmode, 	 
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 CSFmode, 
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 CDFmode, 
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 CXFmode, 
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 CTFmode, 
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214
 BImode, 	 
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216
 BLKmode, 
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 EPmode, 
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MAX_MACHINE_MODE };
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extern char *mode_name[];
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enum mode_class { MODE_RANDOM, MODE_INT, MODE_FLOAT,
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		  MODE_COMPLEX_INT, MODE_COMPLEX_FLOAT, MODE_FUNCTION };
226

    
227
extern enum mode_class mode_class[];
228

    
229
extern int mode_size[];
230

    
231
extern int mode_unit_size[];
232

    
233
typedef union rtunion_def
234
{
235
  int rtint;
236
  char *rtstr;
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  struct rtx_def *rtx;
238
  struct rtvec_def *rtvec;
239
  enum machine_mode rttype;
240
} rtunion;
241

    
242
typedef struct rtx_def
243
{
244

    
245
  enum rtx_code code : 16;
246

    
247
  enum machine_mode mode : 8;
248

    
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  unsigned int jump : 1;
250
  unsigned int call : 1;
251

    
252
  unsigned int unchanging : 1;
253

    
254
  unsigned int volatil : 1;
255

    
256
  unsigned int in_struct : 1;
257

    
258
  unsigned int used : 1;
259

    
260
  unsigned integrated : 1;
261

    
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  rtunion fld[1];
263
} *rtx;
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typedef struct rtvec_def{
266
  unsigned num_elem;		 
267
  rtunion elem[1];
268
} *rtvec;
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enum reg_note { REG_DEAD = 1, REG_INC = 2, REG_EQUIV = 3, REG_WAS_0 = 4,
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		REG_EQUAL = 5, REG_RETVAL = 6, REG_LIBCALL = 7,
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		REG_NONNEG = 8 };
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274
extern char *reg_note_name[];
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extern char *note_insn_name[];
277

    
278
extern rtx rtx_alloc ();
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extern rtvec rtvec_alloc ();
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extern rtx find_reg_note ();
281
extern rtx gen_rtx ();
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extern rtx copy_rtx ();
283
extern rtvec gen_rtvec ();
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extern rtvec gen_rtvec_v ();
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extern rtx gen_reg_rtx ();
286
extern rtx gen_label_rtx ();
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extern rtx gen_inline_header_rtx ();
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extern rtx gen_lowpart ();
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extern rtx gen_highpart ();
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extern int subreg_lowpart_p ();
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extern rtx make_safe_from ();
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extern rtx memory_address ();
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extern rtx get_insns ();
294
extern rtx get_last_insn ();
295
extern rtx start_sequence ();
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extern rtx gen_sequence ();
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extern rtx expand_expr ();
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extern rtx output_constant_def ();
299
extern rtx immed_real_const ();
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extern rtx immed_real_const_1 ();
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extern rtx immed_double_const ();
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extern rtx force_const_double_mem ();
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extern rtx force_const_mem ();
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extern rtx get_parm_real_loc ();
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extern rtx assign_stack_local ();
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extern rtx protect_from_queue ();
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extern void emit_queue ();
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extern rtx emit_move_insn ();
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extern rtx emit_insn ();
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extern rtx emit_jump_insn ();
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extern rtx emit_call_insn ();
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extern rtx emit_call_insn_before ();
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extern rtx emit_insn_before ();
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extern rtx emit_insn_after ();
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extern rtx emit_label ();
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extern rtx emit_barrier ();
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extern rtx emit_note ();
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extern rtx emit_line_note ();
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extern rtx emit_line_note_force ();
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extern rtx prev_real_insn ();
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extern rtx next_real_insn ();
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extern rtx next_nondeleted_insn ();
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extern rtx plus_constant ();
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extern rtx find_equiv_reg ();
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extern rtx delete_insn ();
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extern rtx adj_offsetable_operand ();
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extern int max_parallel;
329

    
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extern int asm_noperands ();
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extern char *decode_asm_operands ();
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extern enum reg_class reg_preferred_class ();
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extern rtx get_first_nonparm_insn ();
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extern rtx pc_rtx;
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extern rtx cc0_rtx;
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extern rtx const0_rtx;
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extern rtx const1_rtx;
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extern rtx fconst0_rtx;
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extern rtx dconst0_rtx;
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extern rtx stack_pointer_rtx;
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extern rtx frame_pointer_rtx;
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extern rtx arg_pointer_rtx;
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extern rtx struct_value_rtx;
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extern rtx struct_value_incoming_rtx;
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extern rtx static_chain_rtx;
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extern rtx static_chain_incoming_rtx;
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352
extern	struct	_iobuf {
353
	int	_cnt;
354
	unsigned char *_ptr;
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	unsigned char *_base;
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	int	_bufsiz;
357
	short	_flag;
358
	char	_file;		 
359
} _iob[];
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361
extern struct _iobuf 	*fopen();
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extern struct _iobuf 	*fdopen();
363
extern struct _iobuf 	*freopen();
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extern struct _iobuf 	*popen();
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extern struct _iobuf 	*tmpfile();
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extern long	ftell();
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extern char	*fgets();
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extern char	*gets();
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370
extern char	*ctermid();
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extern char	*cuserid();
372
extern char	*tempnam();
373
extern char	*tmpnam();
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extern int recog_memoized ();
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377
extern void insn_extract ();
378

    
379
extern rtx recog_operand[];
380

    
381
extern rtx *recog_operand_loc[];
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383
extern rtx *recog_dup_loc[];
384

    
385
extern char recog_dup_num[];
386

    
387
extern char *insn_template[];
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389
extern char *(*insn_outfun[]) ();
390

    
391
extern int insn_n_operands[];
392

    
393
extern int insn_n_dups[];
394

    
395
extern int insn_n_alternatives[];
396

    
397
extern char *insn_operand_constraint[][5 ];
398

    
399
extern char insn_operand_address_p[][5 ];
400

    
401
extern enum machine_mode insn_operand_mode[][5 ];
402

    
403
extern char insn_operand_strict_low[][5 ];
404

    
405
extern int (*insn_operand_predicate[][5 ]) ();
406

    
407
extern int max_regno;
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409
extern short *reg_n_refs;
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411
extern short *reg_n_sets;
412

    
413
extern short *reg_n_deaths;
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415
extern int *reg_n_calls_crossed;
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417
extern int *reg_live_length;
418

    
419
extern short *reg_renumber;
420

    
421
extern char regs_ever_live[56 ];
422

    
423
extern char *reg_names[56 ];
424

    
425
extern short *regno_first_uid;
426

    
427
extern short *regno_last_uid;
428

    
429
extern char *regno_pointer_flag;
430

    
431
extern rtx *regno_reg_rtx;
432

    
433
extern int caller_save_needed;
434

    
435
typedef long HARD_REG_SET[((56  + 32  - 1) / 32 ) ];
436

    
437
extern char fixed_regs[56 ];
438

    
439
extern HARD_REG_SET fixed_reg_set;
440

    
441
extern char call_used_regs[56 ];
442

    
443
extern HARD_REG_SET call_used_reg_set;
444

    
445
extern char call_fixed_regs[56 ];
446

    
447
extern HARD_REG_SET call_fixed_reg_set;
448

    
449
extern char global_regs[56 ];
450

    
451
extern int reg_alloc_order[56 ];
452

    
453
extern HARD_REG_SET reg_class_contents[];
454

    
455
extern int reg_class_size[(int) LIM_REG_CLASSES ];
456

    
457
extern enum reg_class reg_class_superclasses[(int) LIM_REG_CLASSES ][(int) LIM_REG_CLASSES ];
458

    
459
extern enum reg_class reg_class_subclasses[(int) LIM_REG_CLASSES ][(int) LIM_REG_CLASSES ];
460

    
461
extern enum reg_class reg_class_subunion[(int) LIM_REG_CLASSES ][(int) LIM_REG_CLASSES ];
462

    
463
extern double ldexp ();
464

    
465
extern double atof ();
466

    
467
union real_extract 
468
{
469
  double  d;
470
  int i[sizeof (double ) / sizeof (int)];
471
};
472

    
473
static int inequality_comparisons_p ();
474
int strict_memory_address_p ();
475
int memory_address_p ();
476

    
477
int volatile_ok;
478

    
479
rtx recog_addr_dummy;
480

    
481
int which_alternative;
482

    
483
int reload_completed;
484

    
485
void
486
init_recog ()
487
{
488
  volatile_ok = 0;
489
  recog_addr_dummy = gen_rtx (MEM, VOIDmode, 0);
490
}
491

    
492
int
493
recog_memoized (insn)
494
     rtx insn;
495
{
496
  volatile_ok = 1;
497
  if (((insn)->fld[4].rtint)  < 0)
498
    ((insn)->fld[4].rtint)  = recog (((insn)->fld[3].rtx) , insn);
499
  return ((insn)->fld[4].rtint) ;
500
}
501

    
502
int
503
next_insn_tests_no_inequality (insn)
504
     rtx insn;
505
{
506
  register rtx next = ((insn)->fld[2].rtx) ;
507

    
508
  return ((	((next)->code)  == JUMP_INSN
509
	   || 	((next)->code)  == INSN
510
	   || 	((next)->code)  == CALL_INSN)
511
	  && ! inequality_comparisons_p (((next)->fld[3].rtx) ));
512
}
513

    
514
int
515
next_insns_test_no_inequality (insn)
516
     rtx insn;
517
{
518
  register rtx next = ((insn)->fld[2].rtx) ;
519

    
520
  for (;; next = ((next)->fld[2].rtx) )
521
    {
522
      if (	((next)->code)  == CODE_LABEL
523
	  || 	((next)->code)  == BARRIER)
524
	return 1;
525
      if (	((next)->code)  == NOTE)
526
	continue;
527
      if (inequality_comparisons_p (((next)->fld[3].rtx) ))
528
	return 0;
529
      if (	((((next)->fld[3].rtx) )->code)  == SET
530
	  && ((((next)->fld[3].rtx) )->fld[0].rtx)  == cc0_rtx)
531
	return 1;
532
      if (! reg_mentioned_p (cc0_rtx, ((next)->fld[3].rtx) ))
533
	return 1;
534
    }
535
}
536

    
537
static int
538
inequality_comparisons_p (x)
539
     rtx x;
540
{
541
  register char *fmt;
542
  register int len, i;
543
  register enum rtx_code code = 	((x)->code) ;
544

    
545
  switch (code)
546
    {
547
    case REG:
548
    case PC:
549
    case CC0:
550
    case CONST_INT:
551
    case CONST_DOUBLE:
552
    case CONST:
553
    case LABEL_REF:
554
    case SYMBOL_REF:
555
      return 0;
556

    
557
    case LT:
558
    case LTU:
559
    case GT:
560
    case GTU:
561
    case LE:
562
    case LEU:
563
    case GE:
564
    case GEU:
565
      return (((x)->fld[ 0].rtx)  == cc0_rtx || ((x)->fld[ 1].rtx)  == cc0_rtx);
566
    }
567

    
568
  len = 	(rtx_length[(int)(code)]) ;
569
  fmt = 	(rtx_format[(int)(code)]) ;
570

    
571
  for (i = 0; i < len; i++)
572
    {
573
      if (fmt[i] == 'e')
574
	{
575
	  if (inequality_comparisons_p (((x)->fld[ i].rtx) ))
576
	    return 1;
577
	}
578
      else if (fmt[i] == 'E')
579
	{
580
	  register int j;
581
	  for (j = ((x)->fld[ i].rtvec->num_elem)  - 1; j >= 0; j--)
582
	    if (inequality_comparisons_p (((x)->fld[ i].rtvec->elem[ j].rtx) ))
583
	      return 1;
584
	}
585
    }
586
  return 0;
587
}
588

    
589
int
590
general_operand (op, mode)
591
     register rtx op;
592
     enum machine_mode mode;
593
{
594
  register enum rtx_code code = 	((op)->code) ;
595
  int mode_altering_drug = 0;
596

    
597
  if (mode == VOIDmode)
598
    mode = 	((op)->mode) ;
599

    
600
  if ((	((op)->code)  == LABEL_REF || 	((op)->code)  == SYMBOL_REF	|| 	((op)->code)  == CONST_INT	|| 	((op)->code)  == CONST) )
601
    return ((	((op)->mode)  == VOIDmode || 	((op)->mode)  == mode)
602
	    && 1 );
603

    
604
  if (	((op)->mode)  != mode)
605
    return 0;
606

    
607
  while (code == SUBREG)
608
    {
609
      op = ((op)->fld[0].rtx) ;
610
      code = 	((op)->code) ;
611

    
612
    }
613
  if (code == REG)
614
    return 1;
615
  if (code == CONST_DOUBLE)
616
    return 1 ;
617
  if (code == MEM)
618
    {
619
      register rtx y = ((op)->fld[ 0].rtx) ;
620
      if (! volatile_ok && ((op)->volatil) )
621
	return 0;
622
      { { if (( (	(( y)->code)  == LABEL_REF || 	(( y)->code)  == SYMBOL_REF	|| 	(( y)->code)  == CONST_INT	|| 	(( y)->code)  == CONST)  	|| (	(( y)->code)  == REG && (((( y)->fld[0].rtint)  & ~027) != 0) )	|| ((	(( y)->code)  == PRE_DEC || 	(( y)->code)  == POST_INC)	&& (	(((( y)->fld[ 0].rtx) )->code)  == REG) 	&& (((((( y)->fld[ 0].rtx) )->fld[0].rtint)  & ~027) != 0) )	|| (	(( y)->code)  == PLUS	&& (	(((( y)->fld[ 0].rtx) )->code)  == REG)  && (((((( y)->fld[ 0].rtx) )->fld[0].rtint)  & ~027) != 0) 	&& 	(((( y)->fld[ 1].rtx) )->code)  == CONST_INT	&& ((unsigned) (((( y)->fld[ 1].rtx) )->fld[0].rtint)  + 0x8000) < 0x10000)) ) goto   win; } ;	{ { if (	(( y)->code)  == PLUS && (((	(((( y)->fld[ 0].rtx) )->code)  == REG && (((((( y)->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )	|| (	(((( y)->fld[ 0].rtx) )->code)  == SIGN_EXTEND	&& 	(((((( y)->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == REG	&& 	(((((( y)->fld[ 0].rtx) )->fld[ 0].rtx) )->mode)  == HImode	&& (((((((( y)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )) 	|| ((target_flags & 1)  && 	(((( y)->fld[ 0].rtx) )->code)  == MULT	&& ((	(((((( y)->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == REG && (((((((( y)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )	|| (	(((((( y)->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == SIGN_EXTEND	&& 	(((((((( y)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == REG	&& 	(((((((( y)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->mode)  == HImode	&& (((((((((( y)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )) 	&& 	(((((( y)->fld[ 0].rtx) )->fld[ 1].rtx) )->code)  == CONST_INT	&& ((((((( y)->fld[ 0].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 2	|| (((((( y)->fld[ 0].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 4	|| (((((( y)->fld[ 0].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 8))) )	{ { if (	(((( y)->fld[ 1].rtx) )->code)  == LABEL_REF) goto     win;	if (	(((( y)->fld[ 1].rtx) )->code)  == REG && (((((( y)->fld[ 1].rtx) )->fld[0].rtint)  & ~027) != 0) ) goto     win; } ; }	if (	(( y)->code)  == PLUS && (((	(((( y)->fld[ 1].rtx) )->code)  == REG && (((((( y)->fld[ 1].rtx) )->fld[0].rtint)  ^ 020) >= 8) )	|| (	(((( y)->fld[ 1].rtx) )->code)  == SIGN_EXTEND	&& 	(((((( y)->fld[ 1].rtx) )->fld[ 0].rtx) )->code)  == REG	&& 	(((((( y)->fld[ 1].rtx) )->fld[ 0].rtx) )->mode)  == HImode	&& (((((((( y)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )) 	|| ((target_flags & 1)  && 	(((( y)->fld[ 1].rtx) )->code)  == MULT	&& ((	(((((( y)->fld[ 1].rtx) )->fld[ 0].rtx) )->code)  == REG && (((((((( y)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )	|| (	(((((( y)->fld[ 1].rtx) )->fld[ 0].rtx) )->code)  == SIGN_EXTEND	&& 	(((((((( y)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == REG	&& 	(((((((( y)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->mode)  == HImode	&& (((((((((( y)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )) 	&& 	(((((( y)->fld[ 1].rtx) )->fld[ 1].rtx) )->code)  == CONST_INT	&& ((((((( y)->fld[ 1].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 2	|| (((((( y)->fld[ 1].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 4	|| (((((( y)->fld[ 1].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 8))) )	{ { if (	(((( y)->fld[ 0].rtx) )->code)  == LABEL_REF) goto     win;	if (	(((( y)->fld[ 0].rtx) )->code)  == REG && (((((( y)->fld[ 0].rtx) )->fld[0].rtint)  & ~027) != 0) ) goto     win; } ; } } ;	if (	(( y)->code)  == PLUS)	{ if (	(((( y)->fld[ 1].rtx) )->code)  == CONST_INT	&& (unsigned) (((( y)->fld[ 1].rtx) )->fld[0].rtint)  + 0x80 < 0x100)	{ rtx go_temp = (( y)->fld[ 0].rtx) ; { if (	((go_temp)->code)  == PLUS && (((	((((go_temp)->fld[ 0].rtx) )->code)  == REG && ((((((go_temp)->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )	|| (	((((go_temp)->fld[ 0].rtx) )->code)  == SIGN_EXTEND	&& 	((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == REG	&& 	((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->mode)  == HImode	&& ((((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )) 	|| ((target_flags & 1)  && 	((((go_temp)->fld[ 0].rtx) )->code)  == MULT	&& ((	((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == REG && ((((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )	|| (	((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == SIGN_EXTEND	&& 	((((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == REG	&& 	((((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->mode)  == HImode	&& ((((((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )) 	&& 	((((((go_temp)->fld[ 0].rtx) )->fld[ 1].rtx) )->code)  == CONST_INT	&& (((((((go_temp)->fld[ 0].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 2	|| ((((((go_temp)->fld[ 0].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 4	|| ((((((go_temp)->fld[ 0].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 8))) )	{ { if (	((((go_temp)->fld[ 1].rtx) )->code)  == LABEL_REF) goto     win;	if (	((((go_temp)->fld[ 1].rtx) )->code)  == REG && ((((((go_temp)->fld[ 1].rtx) )->fld[0].rtint)  & ~027) != 0) ) goto     win; } ; }	if (	((go_temp)->code)  == PLUS && (((	((((go_temp)->fld[ 1].rtx) )->code)  == REG && ((((((go_temp)->fld[ 1].rtx) )->fld[0].rtint)  ^ 020) >= 8) )	|| (	((((go_temp)->fld[ 1].rtx) )->code)  == SIGN_EXTEND	&& 	((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->code)  == REG	&& 	((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->mode)  == HImode	&& ((((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )) 	|| ((target_flags & 1)  && 	((((go_temp)->fld[ 1].rtx) )->code)  == MULT	&& ((	((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->code)  == REG && ((((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )	|| (	((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->code)  == SIGN_EXTEND	&& 	((((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == REG	&& 	((((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->mode)  == HImode	&& ((((((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )) 	&& 	((((((go_temp)->fld[ 1].rtx) )->fld[ 1].rtx) )->code)  == CONST_INT	&& (((((((go_temp)->fld[ 1].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 2	|| ((((((go_temp)->fld[ 1].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 4	|| ((((((go_temp)->fld[ 1].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 8))) )	{ { if (	((((go_temp)->fld[ 0].rtx) )->code)  == LABEL_REF) goto     win;	if (	((((go_temp)->fld[ 0].rtx) )->code)  == REG && ((((((go_temp)->fld[ 0].rtx) )->fld[0].rtint)  & ~027) != 0) ) goto     win; } ; } } ; }	if (	(((( y)->fld[ 0].rtx) )->code)  == CONST_INT	&& (unsigned) (((( y)->fld[ 0].rtx) )->fld[0].rtint)  + 0x80 < 0x100)	{ rtx go_temp = (( y)->fld[ 1].rtx) ; { if (	((go_temp)->code)  == PLUS && (((	((((go_temp)->fld[ 0].rtx) )->code)  == REG && ((((((go_temp)->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )	|| (	((((go_temp)->fld[ 0].rtx) )->code)  == SIGN_EXTEND	&& 	((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == REG	&& 	((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->mode)  == HImode	&& ((((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )) 	|| ((target_flags & 1)  && 	((((go_temp)->fld[ 0].rtx) )->code)  == MULT	&& ((	((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == REG && ((((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )	|| (	((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == SIGN_EXTEND	&& 	((((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == REG	&& 	((((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->mode)  == HImode	&& ((((((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )) 	&& 	((((((go_temp)->fld[ 0].rtx) )->fld[ 1].rtx) )->code)  == CONST_INT	&& (((((((go_temp)->fld[ 0].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 2	|| ((((((go_temp)->fld[ 0].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 4	|| ((((((go_temp)->fld[ 0].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 8))) )	{ { if (	((((go_temp)->fld[ 1].rtx) )->code)  == LABEL_REF) goto     win;	if (	((((go_temp)->fld[ 1].rtx) )->code)  == REG && ((((((go_temp)->fld[ 1].rtx) )->fld[0].rtint)  & ~027) != 0) ) goto     win; } ; }	if (	((go_temp)->code)  == PLUS && (((	((((go_temp)->fld[ 1].rtx) )->code)  == REG && ((((((go_temp)->fld[ 1].rtx) )->fld[0].rtint)  ^ 020) >= 8) )	|| (	((((go_temp)->fld[ 1].rtx) )->code)  == SIGN_EXTEND	&& 	((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->code)  == REG	&& 	((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->mode)  == HImode	&& ((((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )) 	|| ((target_flags & 1)  && 	((((go_temp)->fld[ 1].rtx) )->code)  == MULT	&& ((	((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->code)  == REG && ((((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )	|| (	((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->code)  == SIGN_EXTEND	&& 	((((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == REG	&& 	((((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->mode)  == HImode	&& ((((((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )) 	&& 	((((((go_temp)->fld[ 1].rtx) )->fld[ 1].rtx) )->code)  == CONST_INT	&& (((((((go_temp)->fld[ 1].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 2	|| ((((((go_temp)->fld[ 1].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 4	|| ((((((go_temp)->fld[ 1].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 8))) )	{ { if (	((((go_temp)->fld[ 0].rtx) )->code)  == LABEL_REF) goto     win;	if (	((((go_temp)->fld[ 0].rtx) )->code)  == REG && ((((((go_temp)->fld[ 0].rtx) )->fld[0].rtint)  & ~027) != 0) ) goto     win; } ; } } ; } } } ; } ;
623
    }
624
  return 0;
625

    
626
 win:
627
  if (mode_altering_drug)
628
    return ! mode_dependent_address_p (((op)->fld[ 0].rtx) );
629
  return 1;
630
}
631

    
632
int
633
address_operand (op, mode)
634
     register rtx op;
635
     enum machine_mode mode;
636
{
637
  return memory_address_p (mode, op);
638
}
639

    
640
int
641
register_operand (op, mode)
642
     register rtx op;
643
     enum machine_mode mode;
644
{
645
  if (	((op)->mode)  != mode && mode != VOIDmode)
646
    return 0;
647

    
648
  if (	((op)->code)  == SUBREG)
649
    {
650

    
651
      if (! reload_completed)
652
	return general_operand (op, mode);
653
    }
654

    
655
  while (	((op)->code)  == SUBREG)
656
    op = ((op)->fld[0].rtx) ;
657

    
658
  return 	((op)->code)  == REG;
659
}
660

    
661
int
662
immediate_operand (op, mode)
663
     register rtx op;
664
     enum machine_mode mode;
665
{
666
  return (((	((op)->code)  == LABEL_REF || 	((op)->code)  == SYMBOL_REF	|| 	((op)->code)  == CONST_INT	|| 	((op)->code)  == CONST) 
667
	   || (	((op)->code)  == CONST_DOUBLE
668
	       && (	((op)->mode)  == mode || mode == VOIDmode)))
669
	  && 1 );
670
}
671

    
672
int
673
nonimmediate_operand (op, mode)
674
     register rtx op;
675
     enum machine_mode mode;
676
{
677
  return (general_operand (op, mode)
678
	  && ! (	((op)->code)  == LABEL_REF || 	((op)->code)  == SYMBOL_REF	|| 	((op)->code)  == CONST_INT	|| 	((op)->code)  == CONST)  && 	((op)->code)  != CONST_DOUBLE);
679
}
680

    
681
int
682
nonmemory_operand (op, mode)
683
     register rtx op;
684
     enum machine_mode mode;
685
{
686
  if ((	((op)->code)  == LABEL_REF || 	((op)->code)  == SYMBOL_REF	|| 	((op)->code)  == CONST_INT	|| 	((op)->code)  == CONST)  || 	((op)->code)  == CONST_DOUBLE)
687
    return ((	((op)->mode)  == VOIDmode || 	((op)->mode)  == mode)
688
	    && 1 );
689

    
690
  if (	((op)->mode)  != mode && mode != VOIDmode)
691
    return 0;
692

    
693
  if (	((op)->code)  == SUBREG)
694
    {
695

    
696
      if (! reload_completed)
697
	return general_operand (op, mode);
698
    }
699

    
700
  while (	((op)->code)  == SUBREG)
701
    op = ((op)->fld[0].rtx) ;
702

    
703
  return 	((op)->code)  == REG;
704
}
705

    
706
int
707
push_operand (op, mode)
708
     rtx op;
709
     enum machine_mode mode;
710
{
711
  if (	((op)->code)  != MEM)
712
    return 0;
713

    
714
  if (	((op)->mode)  != mode)
715
    return 0;
716

    
717
  op = ((op)->fld[ 0].rtx) ;
718

    
719
  if (	((op)->code)  != PRE_DEC)
720
    return 0;
721

    
722
  return ((op)->fld[ 0].rtx)  == stack_pointer_rtx;
723
}
724

    
725
int
726
memory_address_p (mode, addr)
727
     enum machine_mode mode;
728
     register rtx addr;
729
{
730
  { { if (( (	(( addr)->code)  == LABEL_REF || 	(( addr)->code)  == SYMBOL_REF	|| 	(( addr)->code)  == CONST_INT	|| 	(( addr)->code)  == CONST)  	|| (	(( addr)->code)  == REG && (((( addr)->fld[0].rtint)  & ~027) != 0) )	|| ((	(( addr)->code)  == PRE_DEC || 	(( addr)->code)  == POST_INC)	&& (	(((( addr)->fld[ 0].rtx) )->code)  == REG) 	&& (((((( addr)->fld[ 0].rtx) )->fld[0].rtint)  & ~027) != 0) )	|| (	(( addr)->code)  == PLUS	&& (	(((( addr)->fld[ 0].rtx) )->code)  == REG)  && (((((( addr)->fld[ 0].rtx) )->fld[0].rtint)  & ~027) != 0) 	&& 	(((( addr)->fld[ 1].rtx) )->code)  == CONST_INT	&& ((unsigned) (((( addr)->fld[ 1].rtx) )->fld[0].rtint)  + 0x8000) < 0x10000)) ) goto   win; } ;	{ { if (	(( addr)->code)  == PLUS && (((	(((( addr)->fld[ 0].rtx) )->code)  == REG && (((((( addr)->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )	|| (	(((( addr)->fld[ 0].rtx) )->code)  == SIGN_EXTEND	&& 	(((((( addr)->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == REG	&& 	(((((( addr)->fld[ 0].rtx) )->fld[ 0].rtx) )->mode)  == HImode	&& (((((((( addr)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )) 	|| ((target_flags & 1)  && 	(((( addr)->fld[ 0].rtx) )->code)  == MULT	&& ((	(((((( addr)->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == REG && (((((((( addr)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )	|| (	(((((( addr)->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == SIGN_EXTEND	&& 	(((((((( addr)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == REG	&& 	(((((((( addr)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->mode)  == HImode	&& (((((((((( addr)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )) 	&& 	(((((( addr)->fld[ 0].rtx) )->fld[ 1].rtx) )->code)  == CONST_INT	&& ((((((( addr)->fld[ 0].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 2	|| (((((( addr)->fld[ 0].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 4	|| (((((( addr)->fld[ 0].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 8))) )	{ { if (	(((( addr)->fld[ 1].rtx) )->code)  == LABEL_REF) goto     win;	if (	(((( addr)->fld[ 1].rtx) )->code)  == REG && (((((( addr)->fld[ 1].rtx) )->fld[0].rtint)  & ~027) != 0) ) goto     win; } ; }	if (	(( addr)->code)  == PLUS && (((	(((( addr)->fld[ 1].rtx) )->code)  == REG && (((((( addr)->fld[ 1].rtx) )->fld[0].rtint)  ^ 020) >= 8) )	|| (	(((( addr)->fld[ 1].rtx) )->code)  == SIGN_EXTEND	&& 	(((((( addr)->fld[ 1].rtx) )->fld[ 0].rtx) )->code)  == REG	&& 	(((((( addr)->fld[ 1].rtx) )->fld[ 0].rtx) )->mode)  == HImode	&& (((((((( addr)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )) 	|| ((target_flags & 1)  && 	(((( addr)->fld[ 1].rtx) )->code)  == MULT	&& ((	(((((( addr)->fld[ 1].rtx) )->fld[ 0].rtx) )->code)  == REG && (((((((( addr)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )	|| (	(((((( addr)->fld[ 1].rtx) )->fld[ 0].rtx) )->code)  == SIGN_EXTEND	&& 	(((((((( addr)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == REG	&& 	(((((((( addr)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->mode)  == HImode	&& (((((((((( addr)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )) 	&& 	(((((( addr)->fld[ 1].rtx) )->fld[ 1].rtx) )->code)  == CONST_INT	&& ((((((( addr)->fld[ 1].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 2	|| (((((( addr)->fld[ 1].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 4	|| (((((( addr)->fld[ 1].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 8))) )	{ { if (	(((( addr)->fld[ 0].rtx) )->code)  == LABEL_REF) goto     win;	if (	(((( addr)->fld[ 0].rtx) )->code)  == REG && (((((( addr)->fld[ 0].rtx) )->fld[0].rtint)  & ~027) != 0) ) goto     win; } ; } } ;	if (	(( addr)->code)  == PLUS)	{ if (	(((( addr)->fld[ 1].rtx) )->code)  == CONST_INT	&& (unsigned) (((( addr)->fld[ 1].rtx) )->fld[0].rtint)  + 0x80 < 0x100)	{ rtx go_temp = (( addr)->fld[ 0].rtx) ; { if (	((go_temp)->code)  == PLUS && (((	((((go_temp)->fld[ 0].rtx) )->code)  == REG && ((((((go_temp)->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )	|| (	((((go_temp)->fld[ 0].rtx) )->code)  == SIGN_EXTEND	&& 	((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == REG	&& 	((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->mode)  == HImode	&& ((((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )) 	|| ((target_flags & 1)  && 	((((go_temp)->fld[ 0].rtx) )->code)  == MULT	&& ((	((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == REG && ((((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )	|| (	((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == SIGN_EXTEND	&& 	((((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == REG	&& 	((((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->mode)  == HImode	&& ((((((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )) 	&& 	((((((go_temp)->fld[ 0].rtx) )->fld[ 1].rtx) )->code)  == CONST_INT	&& (((((((go_temp)->fld[ 0].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 2	|| ((((((go_temp)->fld[ 0].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 4	|| ((((((go_temp)->fld[ 0].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 8))) )	{ { if (	((((go_temp)->fld[ 1].rtx) )->code)  == LABEL_REF) goto     win;	if (	((((go_temp)->fld[ 1].rtx) )->code)  == REG && ((((((go_temp)->fld[ 1].rtx) )->fld[0].rtint)  & ~027) != 0) ) goto     win; } ; }	if (	((go_temp)->code)  == PLUS && (((	((((go_temp)->fld[ 1].rtx) )->code)  == REG && ((((((go_temp)->fld[ 1].rtx) )->fld[0].rtint)  ^ 020) >= 8) )	|| (	((((go_temp)->fld[ 1].rtx) )->code)  == SIGN_EXTEND	&& 	((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->code)  == REG	&& 	((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->mode)  == HImode	&& ((((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )) 	|| ((target_flags & 1)  && 	((((go_temp)->fld[ 1].rtx) )->code)  == MULT	&& ((	((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->code)  == REG && ((((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )	|| (	((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->code)  == SIGN_EXTEND	&& 	((((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == REG	&& 	((((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->mode)  == HImode	&& ((((((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )) 	&& 	((((((go_temp)->fld[ 1].rtx) )->fld[ 1].rtx) )->code)  == CONST_INT	&& (((((((go_temp)->fld[ 1].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 2	|| ((((((go_temp)->fld[ 1].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 4	|| ((((((go_temp)->fld[ 1].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 8))) )	{ { if (	((((go_temp)->fld[ 0].rtx) )->code)  == LABEL_REF) goto     win;	if (	((((go_temp)->fld[ 0].rtx) )->code)  == REG && ((((((go_temp)->fld[ 0].rtx) )->fld[0].rtint)  & ~027) != 0) ) goto     win; } ; } } ; }	if (	(((( addr)->fld[ 0].rtx) )->code)  == CONST_INT	&& (unsigned) (((( addr)->fld[ 0].rtx) )->fld[0].rtint)  + 0x80 < 0x100)	{ rtx go_temp = (( addr)->fld[ 1].rtx) ; { if (	((go_temp)->code)  == PLUS && (((	((((go_temp)->fld[ 0].rtx) )->code)  == REG && ((((((go_temp)->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )	|| (	((((go_temp)->fld[ 0].rtx) )->code)  == SIGN_EXTEND	&& 	((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == REG	&& 	((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->mode)  == HImode	&& ((((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )) 	|| ((target_flags & 1)  && 	((((go_temp)->fld[ 0].rtx) )->code)  == MULT	&& ((	((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == REG && ((((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )	|| (	((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == SIGN_EXTEND	&& 	((((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == REG	&& 	((((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->mode)  == HImode	&& ((((((((((go_temp)->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )) 	&& 	((((((go_temp)->fld[ 0].rtx) )->fld[ 1].rtx) )->code)  == CONST_INT	&& (((((((go_temp)->fld[ 0].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 2	|| ((((((go_temp)->fld[ 0].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 4	|| ((((((go_temp)->fld[ 0].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 8))) )	{ { if (	((((go_temp)->fld[ 1].rtx) )->code)  == LABEL_REF) goto     win;	if (	((((go_temp)->fld[ 1].rtx) )->code)  == REG && ((((((go_temp)->fld[ 1].rtx) )->fld[0].rtint)  & ~027) != 0) ) goto     win; } ; }	if (	((go_temp)->code)  == PLUS && (((	((((go_temp)->fld[ 1].rtx) )->code)  == REG && ((((((go_temp)->fld[ 1].rtx) )->fld[0].rtint)  ^ 020) >= 8) )	|| (	((((go_temp)->fld[ 1].rtx) )->code)  == SIGN_EXTEND	&& 	((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->code)  == REG	&& 	((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->mode)  == HImode	&& ((((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )) 	|| ((target_flags & 1)  && 	((((go_temp)->fld[ 1].rtx) )->code)  == MULT	&& ((	((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->code)  == REG && ((((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )	|| (	((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->code)  == SIGN_EXTEND	&& 	((((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->code)  == REG	&& 	((((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->mode)  == HImode	&& ((((((((((go_temp)->fld[ 1].rtx) )->fld[ 0].rtx) )->fld[ 0].rtx) )->fld[0].rtint)  ^ 020) >= 8) )) 	&& 	((((((go_temp)->fld[ 1].rtx) )->fld[ 1].rtx) )->code)  == CONST_INT	&& (((((((go_temp)->fld[ 1].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 2	|| ((((((go_temp)->fld[ 1].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 4	|| ((((((go_temp)->fld[ 1].rtx) )->fld[ 1].rtx) )->fld[0].rtint)  == 8))) )	{ { if (	((((go_temp)->fld[ 0].rtx) )->code)  == LABEL_REF) goto     win;	if (	((((go_temp)->fld[ 0].rtx) )->code)  == REG && ((((((go_temp)->fld[ 0].rtx) )->fld[0].rtint)  & ~027) != 0) ) goto     win; } ; } } ; } } } ; } ;
731
  return 0;
732

    
733
 win:
734
  return 1;
735
}
736

    
737
int
738
memory_operand (op, mode)
739
     register rtx op;
740
     enum machine_mode mode;
741
{
742
  int mode_altering_drug = 0;
743

    
744
  if (! reload_completed)
745

    
746
    return 	((op)->code)  == MEM && general_operand (op, mode);
747

    
748
  while (	((op)->code)  == SUBREG)
749
    {
750
      op = ((op)->fld[0].rtx) ;
751
      mode_altering_drug = 1;
752
    }
753

    
754
  return (	((op)->code)  == MEM && general_operand (op, mode)
755
	  && ! (mode_altering_drug
756
		&& mode_dependent_address_p (((op)->fld[ 0].rtx) )));
757
}
758

    
759
int
760
indirect_operand (op, mode)
761
     register rtx op;
762
     enum machine_mode mode;
763
{
764
  return (	((op)->mode)  == mode && memory_operand (op, mode)
765
	  && general_operand (((op)->fld[ 0].rtx) , SImode ));
766
}
767

    
768
int
769
asm_noperands (body)
770
     rtx body;
771
{
772
  if (	((body)->code)  == ASM_OPERANDS)
773
    return ((body)->fld[ 3].rtvec->num_elem) ;
774
  if (	((body)->code)  == SET && 	((((body)->fld[1].rtx) )->code)  == ASM_OPERANDS)
775
    return ((((body)->fld[1].rtx) )->fld[ 3].rtvec->num_elem)  + 1;
776
  else if (	((body)->code)  == PARALLEL
777
	   && 	((((body)->fld[ 0].rtvec->elem[ 0].rtx) )->code)  == SET
778
	   && 	((((((body)->fld[ 0].rtvec->elem[ 0].rtx) )->fld[1].rtx) )->code)  == ASM_OPERANDS)
779
    {
780

    
781
      int i;
782
      int n_sets;
783

    
784
      for (i = ((body)->fld[ 0].rtvec->num_elem) ; i > 0; i--)
785
	{
786
	  if (	((((body)->fld[ 0].rtvec->elem[ i - 1].rtx) )->code)  == SET)
787
	    break;
788
	  if (	((((body)->fld[ 0].rtvec->elem[ i - 1].rtx) )->code)  != CLOBBER)
789
	    return -1;
790
	}
791

    
792
      n_sets = i;
793

    
794
      for (i = 0; i < n_sets; i++)
795
	{
796
	  rtx elt = ((body)->fld[ 0].rtvec->elem[ i].rtx) ;
797
	  if (	((elt)->code)  != SET)
798
	    return -1;
799
	  if (	((((elt)->fld[1].rtx) )->code)  != ASM_OPERANDS)
800
	    return -1;
801

    
802
	  if (((((elt)->fld[1].rtx) )->fld[ 3].rtvec) 
803
	      != ((((((body)->fld[ 0].rtvec->elem[ 0].rtx) )->fld[1].rtx) )->fld[ 3].rtvec) )
804
	    return -1;
805
	}
806
      return ((((((body)->fld[ 0].rtvec->elem[ 0].rtx) )->fld[1].rtx) )->fld[ 3].rtvec->num_elem)  + n_sets;
807
    }
808
  else if (	((body)->code)  == PARALLEL
809
	   && 	((((body)->fld[ 0].rtvec->elem[ 0].rtx) )->code)  == ASM_OPERANDS)
810
    {
811

    
812
      int i;
813
      int n_sets;
814

    
815
      for (i = ((body)->fld[ 0].rtvec->num_elem)  - 1; i > 0; i--)
816
	if (	((((body)->fld[ 0].rtvec->elem[ i].rtx) )->code)  != CLOBBER)
817
	  return -1;
818

    
819
      return ((((body)->fld[ 0].rtvec->elem[ 0].rtx) )->fld[ 3].rtvec->num_elem) ;
820
    }
821
  else
822
    return -1;
823
}
824

    
825
char *
826
decode_asm_operands (body, operands, operand_locs, constraints, modes)
827
     rtx body;
828
     rtx *operands;
829
     rtx **operand_locs;
830
     char **constraints;
831
     enum machine_mode *modes;
832
{
833
  register int i;
834
  int noperands;
835
  char *template = 0;
836

    
837
  if (	((body)->code)  == SET && 	((((body)->fld[1].rtx) )->code)  == ASM_OPERANDS)
838
    {
839
      rtx asmop = ((body)->fld[1].rtx) ;
840

    
841
      noperands = ((asmop)->fld[ 3].rtvec->num_elem)  + 1;
842

    
843
      for (i = 1; i < noperands; i++)
844
	{
845
	  if (operand_locs)
846
	    operand_locs[i] = &((asmop)->fld[ 3].rtvec->elem[ i - 1].rtx) ;
847
	  if (operands)
848
	    operands[i] = ((asmop)->fld[ 3].rtvec->elem[ i - 1].rtx) ;
849
	  if (constraints)
850
	    constraints[i] = ((((asmop)->fld[ 4].rtvec->elem[ i - 1].rtx) )->fld[ 0].rtstr) ;
851
	  if (modes)
852
	    modes[i] = 	((((asmop)->fld[ 4].rtvec->elem[ i - 1].rtx) )->mode) ;
853
	}
854

    
855
      if (operands)
856
	operands[0] = ((body)->fld[0].rtx) ;
857
      if (operand_locs)
858
	operand_locs[0] = &((body)->fld[0].rtx) ;
859
      if (constraints)
860
	constraints[0] = ((asmop)->fld[ 1].rtstr) ;
861
      if (modes)
862
	modes[0] = 	((((body)->fld[0].rtx) )->mode) ;
863
      template = ((asmop)->fld[ 0].rtstr) ;
864
    }
865
  else if (	((body)->code)  == ASM_OPERANDS)
866
    {
867
      rtx asmop = body;
868

    
869
      noperands = ((asmop)->fld[ 3].rtvec->num_elem) ;
870

    
871
      for (i = 0; i < noperands; i++)
872
	{
873
	  if (operand_locs)
874
	    operand_locs[i] = &((asmop)->fld[ 3].rtvec->elem[ i].rtx) ;
875
	  if (operands)
876
	    operands[i] = ((asmop)->fld[ 3].rtvec->elem[ i].rtx) ;
877
	  if (constraints)
878
	    constraints[i] = ((((asmop)->fld[ 4].rtvec->elem[ i].rtx) )->fld[ 0].rtstr) ;
879
	  if (modes)
880
	    modes[i] = 	((((asmop)->fld[ 4].rtvec->elem[ i].rtx) )->mode) ;
881
	}
882
      template = ((asmop)->fld[ 0].rtstr) ;
883
    }
884
  else if (	((body)->code)  == PARALLEL
885
	   && 	((((body)->fld[ 0].rtvec->elem[ 0].rtx) )->code)  == SET)
886
    {
887
      rtx asmop = ((((body)->fld[ 0].rtvec->elem[ 0].rtx) )->fld[1].rtx) ;
888
      int nparallel = ((body)->fld[ 0].rtvec->num_elem) ;  
889
      int nin = ((asmop)->fld[ 3].rtvec->num_elem) ;
890
      int nout = 0;		 
891

    
892
      for (i = 0; i < nparallel; i++)
893
	{
894
	  if (	((((body)->fld[ 0].rtvec->elem[ i].rtx) )->code)  == CLOBBER)
895
	    break;		 
896
	  if (operands)
897
	    operands[i] = ((((body)->fld[ 0].rtvec->elem[ i].rtx) )->fld[0].rtx) ;
898
	  if (operand_locs)
899
	    operand_locs[i] = &((((body)->fld[ 0].rtvec->elem[ i].rtx) )->fld[0].rtx) ;
900
	  if (constraints)
901
	    constraints[i] = ((((((body)->fld[ 0].rtvec->elem[ i].rtx) )->fld[1].rtx) )->fld[ 1].rtstr) ;
902
	  if (modes)
903
	    modes[i] = 	((((((body)->fld[ 0].rtvec->elem[ i].rtx) )->fld[0].rtx) )->mode) ;
904
	  nout++;
905
	}
906

    
907
      for (i = 0; i < nin; i++)
908
	{
909
	  if (operand_locs)
910
	    operand_locs[i + nout] = &((asmop)->fld[ 3].rtvec->elem[ i].rtx) ;
911
	  if (operands)
912
	    operands[i + nout] = ((asmop)->fld[ 3].rtvec->elem[ i].rtx) ;
913
	  if (constraints)
914
	    constraints[i + nout] = ((((asmop)->fld[ 4].rtvec->elem[ i].rtx) )->fld[ 0].rtstr) ;
915
	  if (modes)
916
	    modes[i + nout] = 	((((asmop)->fld[ 4].rtvec->elem[ i].rtx) )->mode) ;
917
	}
918

    
919
      template = ((asmop)->fld[ 0].rtstr) ;
920
    }
921
  else if (	((body)->code)  == PARALLEL
922
	   && 	((((body)->fld[ 0].rtvec->elem[ 0].rtx) )->code)  == ASM_OPERANDS)
923
    {
924

    
925
      rtx asmop = ((body)->fld[ 0].rtvec->elem[ 0].rtx) ;
926
      int nin = ((asmop)->fld[ 3].rtvec->num_elem) ;
927

    
928
      for (i = 0; i < nin; i++)
929
	{
930
	  if (operand_locs)
931
	    operand_locs[i] = &((asmop)->fld[ 3].rtvec->elem[ i].rtx) ;
932
	  if (operands)
933
	    operands[i] = ((asmop)->fld[ 3].rtvec->elem[ i].rtx) ;
934
	  if (constraints)
935
	    constraints[i] = ((((asmop)->fld[ 4].rtvec->elem[ i].rtx) )->fld[ 0].rtstr) ;
936
	  if (modes)
937
	    modes[i] = 	((((asmop)->fld[ 4].rtvec->elem[ i].rtx) )->mode) ;
938
	}
939

    
940
      template = ((asmop)->fld[ 0].rtstr) ;
941
    }
942

    
943
  return template;
944
}
945
extern rtx plus_constant ();
946
extern rtx copy_rtx ();
947

    
948
static rtx *
949
find_constant_term_loc (p)
950
     rtx *p;
951
{
952
  register rtx *tem;
953
  register enum rtx_code code = 	((*p)->code) ;
954

    
955
  if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF
956
      || code == CONST)
957
    return p;
958

    
959
  if (	((*p)->code)  != PLUS)
960
    return 0;
961

    
962
  if (((*p)->fld[ 0].rtx)  && (	((((*p)->fld[ 0].rtx) )->code)  == LABEL_REF || 	((((*p)->fld[ 0].rtx) )->code)  == SYMBOL_REF	|| 	((((*p)->fld[ 0].rtx) )->code)  == CONST_INT	|| 	((((*p)->fld[ 0].rtx) )->code)  == CONST) 
963
      && ((*p)->fld[ 1].rtx)  && (	((((*p)->fld[ 1].rtx) )->code)  == LABEL_REF || 	((((*p)->fld[ 1].rtx) )->code)  == SYMBOL_REF	|| 	((((*p)->fld[ 1].rtx) )->code)  == CONST_INT	|| 	((((*p)->fld[ 1].rtx) )->code)  == CONST) )
964
    return p;
965

    
966
  if (((*p)->fld[ 0].rtx)  != 0)
967
    {
968
      tem = find_constant_term_loc (&((*p)->fld[ 0].rtx) );
969
      if (tem != 0)
970
	return tem;
971
    }
972

    
973
  if (((*p)->fld[ 1].rtx)  != 0)
974
    {
975
      tem = find_constant_term_loc (&((*p)->fld[ 1].rtx) );
976
      if (tem != 0)
977
	return tem;
978
    }
979

    
980
  return 0;
981
}
982

    
983
int
984
offsetable_memref_p (op)
985
     rtx op;
986
{
987
  return ((	((op)->code)  == MEM)
988
	  && offsetable_address_p (1, 	((op)->mode) , ((op)->fld[ 0].rtx) ));
989
}
990

    
991
int
992
offsetable_address_p (strictp, mode, y)
993
     int strictp;
994
     enum machine_mode mode;
995
     register rtx y;
996
{
997
  register enum rtx_code ycode = 	((y)->code) ;
998
  register rtx z;
999
  rtx y1 = y;
1000
  rtx *y2;
1001
  int (*addressp) () = (strictp ? strict_memory_address_p : memory_address_p);
1002

    
1003
  if ( (	((y)->code)  == LABEL_REF || 	((y)->code)  == SYMBOL_REF	|| 	((y)->code)  == CONST_INT	|| 	((y)->code)  == CONST)  )
1004
    return 1;
1005

    
1006
  if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1)))
1007
    {
1008
      int old = ((y1 = *y2)->fld[0].rtint) ;
1009
      int good;
1010
      ((y1)->fld[0].rtint)  += 	(mode_size[(int)(mode)])  - 1;
1011
      good = (*addressp) (mode, y);
1012
      ((y1)->fld[0].rtint)  = old;
1013
      return good;
1014
    }
1015

    
1016
  if (ycode == PRE_DEC || ycode == PRE_INC
1017
      || ycode == POST_DEC || ycode == POST_INC)
1018
    return 0;
1019

    
1020
  z = plus_constant (y, 	(mode_size[(int)(mode)])  - 1);
1021

    
1022
  return (*addressp) (mode, z);
1023
}
1024

    
1025
int
1026
mode_dependent_address_p (addr)
1027
     rtx addr;
1028
{
1029
  if (	((addr)->code)  == POST_INC || 	((addr)->code)  == PRE_DEC) goto  win ;
1030
  return 0;
1031
 win:
1032
  return 1;
1033
}
1034

    
1035
int
1036
mode_independent_operand (op, mode)
1037
     enum machine_mode mode;
1038
     rtx op;
1039
{
1040
  rtx addr;
1041

    
1042
  if (! general_operand (op, mode))
1043
    return 0;
1044

    
1045
  if (	((op)->code)  != MEM)
1046
    return 1;
1047

    
1048
  addr = ((op)->fld[ 0].rtx) ;
1049
  if (	((addr)->code)  == POST_INC || 	((addr)->code)  == PRE_DEC) goto  lose ;
1050
  return 1;
1051
 lose:
1052
  return 0;
1053
}
1054

    
1055
rtx
1056
adj_offsetable_operand (op, offset)
1057
     rtx op;
1058
     int offset;
1059
{
1060
  register enum rtx_code code = 	((op)->code) ;
1061

    
1062
  if (code == MEM) 
1063
    {
1064
      register rtx y = ((op)->fld[ 0].rtx) ;
1065

    
1066
      if ( (	((y)->code)  == LABEL_REF || 	((y)->code)  == SYMBOL_REF	|| 	((y)->code)  == CONST_INT	|| 	((y)->code)  == CONST)  )
1067
	return gen_rtx (MEM, 	((op)->mode) , plus_constant (y, offset));
1068

    
1069
      if (	((y)->code)  == PLUS)
1070
	{
1071
	  rtx z = y;
1072
	  register rtx *const_loc;
1073

    
1074
	  op = copy_rtx (op);
1075
	  z = ((op)->fld[ 0].rtx) ;
1076
	  const_loc = find_constant_term_loc (&z);
1077
	  if (const_loc)
1078
	    {
1079
	      *const_loc = plus_constant (*const_loc, offset);
1080
	      return op;
1081
	    }
1082
	}
1083

    
1084
      return gen_rtx (MEM, 	((op)->mode) , plus_constant (y, offset));
1085
    }
1086
  abort ();
1087
}
1088

    
1089
struct funny_match
1090
{
1091
  int this, other;
1092
};
1093

    
1094
int
1095
constrain_operands (insn_code_num)
1096
     int insn_code_num;
1097
{
1098
  char *constraints[5 ];
1099
  register int c;
1100
  int noperands = insn_n_operands[insn_code_num];
1101

    
1102
  struct funny_match funny_match[5 ];
1103
  int funny_match_index;
1104
  int nalternatives = insn_n_alternatives[insn_code_num];
1105

    
1106
  if (noperands == 0 || nalternatives == 0)
1107
    return 1;
1108

    
1109
  for (c = 0; c < noperands; c++)
1110
    constraints[c] = insn_operand_constraint[insn_code_num][c];
1111

    
1112
  which_alternative = 0;
1113

    
1114
  while (which_alternative < nalternatives)
1115
    {
1116
      register int opno;
1117
      int lose = 0;
1118
      funny_match_index = 0;
1119

    
1120
      for (opno = 0; opno < noperands; opno++)
1121
	{
1122
	  register rtx op = recog_operand[opno];
1123
	  register char *p = constraints[opno];
1124
	  int win = 0;
1125
	  int val;
1126

    
1127
	  while (	((op)->code)  == SUBREG)
1128
	    abort ();
1129

    
1130
	  if (*p == 0 || *p == ',')
1131
	    win = 1;
1132

    
1133
	  while (*p && (c = *p++) != ',')
1134
	    switch (c)
1135
	      {
1136
	      case '=':
1137
	      case '+':
1138
	      case '?':
1139
	      case '#':
1140
	      case '!':
1141
	      case '*':
1142
	      case '%':
1143
		break;
1144

    
1145
	      case '0':
1146
	      case '1':
1147
	      case '2':
1148
	      case '3':
1149
	      case '4':
1150

    
1151
		val = operands_match_p (recog_operand[c - '0'],
1152
					recog_operand[opno]);
1153
		if (val != 0)
1154
		  win = 1;
1155

    
1156
		if (val == 2)
1157
		  {
1158
		    funny_match[funny_match_index].this = opno;
1159
		    funny_match[funny_match_index++].other = c - '0';
1160
		  }
1161
		break;
1162

    
1163
	      case 'p':
1164

    
1165
		win = 1;
1166
		break;
1167

    
1168
	      case 'g':
1169

    
1170
		if (GENERAL_REGS == ALL_REGS
1171
		    || 	((op)->code)  != REG
1172
		    || reg_fits_class_p (op, GENERAL_REGS, 0, 	((op)->mode) ))
1173
		  win = 1;
1174
		break;
1175

    
1176
	      case 'r':
1177
		if (	((op)->code)  == REG
1178
		    && (GENERAL_REGS == ALL_REGS
1179
			|| reg_fits_class_p (op, GENERAL_REGS, 0, 	((op)->mode) )))
1180
		  win = 1;
1181
		break;
1182

    
1183
	      case 'm':
1184
		if (	((op)->code)  == MEM)
1185
		  win = 1;
1186
		break;
1187

    
1188
	      case '<':
1189
		if (	((op)->code)  == MEM
1190
		    && (	((((op)->fld[ 0].rtx) )->code)  == PRE_DEC
1191
			|| 	((((op)->fld[ 0].rtx) )->code)  == POST_DEC))
1192
		  win = 1;
1193
		break;
1194

    
1195
	      case '>':
1196
		if (	((op)->code)  == MEM
1197
		    && (	((((op)->fld[ 0].rtx) )->code)  == PRE_INC
1198
			|| 	((((op)->fld[ 0].rtx) )->code)  == POST_INC))
1199
		  win = 1;
1200
		break;
1201

    
1202
	      case 'F':
1203
		if (	((op)->code)  == CONST_DOUBLE)
1204
		  win = 1;
1205
		break;
1206

    
1207
	      case 'G':
1208
	      case 'H':
1209
		if (	((op)->code)  == CONST_DOUBLE
1210
		    && (( c) == 'G' ? ! ((target_flags & 2)  && standard_68881_constant_p (op)) : ( c) == 'H' ? ((target_flags & 0100)  && standard_sun_fpa_constant_p (op)) : 0) )
1211
		  win = 1;
1212
		break;
1213

    
1214
	      case 's':
1215
		if (	((op)->code)  == CONST_INT)
1216
		  break;
1217
	      case 'i':
1218
		if ((	((op)->code)  == LABEL_REF || 	((op)->code)  == SYMBOL_REF	|| 	((op)->code)  == CONST_INT	|| 	((op)->code)  == CONST) )
1219
		  win = 1;
1220
		break;
1221

    
1222
	      case 'n':
1223
		if (	((op)->code)  == CONST_INT)
1224
		  win = 1;
1225
		break;
1226

    
1227
	      case 'I':
1228
	      case 'J':
1229
	      case 'K':
1230
	      case 'L':
1231
	      case 'M':
1232
		if (	((op)->code)  == CONST_INT
1233
		    && (( c) == 'I' ? (((op)->fld[0].rtint) ) > 0 && (((op)->fld[0].rtint) ) <= 8 : ( c) == 'J' ? (((op)->fld[0].rtint) ) >= -0x8000 && (((op)->fld[0].rtint) ) <= 0x7FFF :	( c) == 'K' ? (((op)->fld[0].rtint) ) < -0x80 || (((op)->fld[0].rtint) ) >= 0x80 :	( c) == 'L' ? (((op)->fld[0].rtint) ) < 0 && (((op)->fld[0].rtint) ) >= -8 : 0) )
1234
		  win = 1;
1235
		break;
1236

    
1237
	      case 'o':
1238
		if (offsetable_memref_p (op))
1239
		  win = 1;
1240
		break;
1241

    
1242
	      default:
1243
		if (	((op)->code)  == REG
1244
		    && reg_fits_class_p (op, ((c) == 'a' ? ADDR_REGS :	((c) == 'd' ? DATA_REGS :	((c) == 'f' ? ((target_flags & 2)  ? FP_REGS :	NO_REGS) :	((c) == 'x' ? ((target_flags & 0100)  ? FPA_REGS :	NO_REGS) :	((c) == 'y' ? ((target_flags & 0100)  ? LO_FPA_REGS :	NO_REGS) :	NO_REGS))))) ,
1245
					 0, 	((op)->mode) ))
1246
		  win = 1;
1247
	      }
1248

    
1249
	  constraints[opno] = p;
1250

    
1251
	  if (! win)
1252
	    lose = 1;
1253
	}
1254

    
1255
      if (! lose)
1256
	{
1257
	  while (--funny_match_index >= 0)
1258
	    {
1259
	      recog_operand[funny_match[funny_match_index].other]
1260
		= recog_operand[funny_match[funny_match_index].this];
1261
	    }
1262
	  return 1;
1263
	}
1264

    
1265
      which_alternative++;
1266
    }
1267
  return 0;
1268
}
1269

    
1270
int
1271
reg_fits_class_p (operand, class, offset, mode)
1272
     rtx operand;
1273
     register enum reg_class class;
1274
     int offset;
1275
     enum machine_mode mode;
1276
{
1277
  register int regno = ((operand)->fld[0].rtint) ;
1278
  if (regno < 56 
1279
      && ((reg_class_contents[(int) class])[(
1280
			    regno + offset) / 32 ] & (1 << ((
1281
			    regno + offset) % 32 ))) )
1282
    {
1283
      register int sr;
1284
      regno += offset;
1285
      for (sr = ((regno) >= 16 ? 1	: ((	(mode_size[(int)( mode)])  + 4  - 1) / 4 ))  - 1;
1286
	   sr > 0; sr--)
1287
	if (! ((reg_class_contents[(int) class])[(
1288
				 regno + sr) / 32 ] & (1 << ((
1289
				 regno + sr) % 32 ))) )
1290
	  break;
1291
      return sr == 0;
1292
    }
1293
  return 0;
1294
}
1295

    
1296